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Commit 7d54a904 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Apply post-sync write for pipe control invalidates 



When invalidating the TLBs it is documentated as requiring a post-sync
write. Failure to do so seems to result in a GPU hang.

Exposure to this hang on IVB seems to be a result of removing the extra
stalls required for SNB pipecontrol workarounds:

commit 6c6cf5aa
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Jul 20 18:02:28 2012 +0100

    drm/i915: Only apply the SNB pipe control w/a to gen6

Note: Manually switch the pipe_control cmd to 4 dwords to avoid a
(silent) functional conflict with -next. This way will get a loud (but
conflict with next (since the scratch_addr has been deleted there).

Reported-and-tested-by: default avatar <yex.tian@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53322


Acked-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
[danvet: added note about merge conflict with -next.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 35a38556

drivers/gpu/drm/i915/intel_ringbuffer.c

+23 −18
Original line number Diff line number Diff line
@@ -227,31 +227,36 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, 
	 * number of bits based on the write domains has little performance

	 * impact.

	 */

	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		/*

		 * Ensure that any following seqno writes only happen

		 * when the render cache is indeed flushed.

		 */

		flags |= PIPE_CONTROL_CS_STALL;

	}

	if (invalidate_domains) {

		flags |= PIPE_CONTROL_TLB_INVALIDATE;

		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;

	flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;

		/*

	 * Ensure that any following seqno writes only happen when the render

	 * cache is indeed flushed (but only if the caller actually wants that).

		 * TLB invalidate requires a post-sync write.

		 */

	if (flush_domains)

		flags |= PIPE_CONTROL_CS_STALL;

		flags |= PIPE_CONTROL_QW_WRITE;

	}



	ret = intel_ring_begin(ring, 6);

	ret = intel_ring_begin(ring, 4);

	if (ret)

		return ret;



	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));

	intel_ring_emit(ring, flags);

	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, 0); /* lower dword */

	intel_ring_emit(ring, 0); /* uppwer dword */

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_emit(ring, 0);

	intel_ring_advance(ring);



	return 0;