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Commit 7d30e8b3 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: EXYNOS4: Add EXYNOS4 CPU initialization support 



This patch adds EXYNOS4 CPU support files in mach-exynos4,
and basically they are moved from mach-s5pv310 so that it
can support Samsung's new CPU name, EXYNOS4.
The EXYNOS4 ingegrates a ARM Cortex A9 multi-core.

Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent f5412be5

arch/arm/mach-s5pv310/cpu.c→arch/arm/mach-exynos4/cpu.c

+44 −43
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5pv310/cpu.c

/* linux/arch/arm/mach-exynos4/cpu.c

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@ 


#include <plat/cpu.h>

#include <plat/clock.h>

#include <plat/s5pv310.h>

#include <plat/exynos4.h>

#include <plat/sdhci.h>



#include <mach/regs-irq.h>
@@ -29,55 +29,55 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base, 
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);



/* Initial IO mappings */

static struct map_desc s5pv310_iodesc[] __initdata = {

static struct map_desc exynos4_iodesc[] __initdata = {

	{

		.virtual	= (unsigned long)S5P_VA_SYSRAM,

		.pfn		= __phys_to_pfn(S5PV310_PA_SYSRAM),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_CMU,

		.pfn		= __phys_to_pfn(S5PV310_PA_CMU),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),

		.length		= SZ_128K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_PMU,

		.pfn		= __phys_to_pfn(S5PV310_PA_PMU),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),

		.length		= SZ_64K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,

		.pfn		= __phys_to_pfn(S5PV310_PA_COMBINER),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,

		.pfn		= __phys_to_pfn(S5PV310_PA_COREPERI),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),

		.length		= SZ_8K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_L2CC,

		.pfn		= __phys_to_pfn(S5PV310_PA_L2CC),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO1,

		.pfn		= __phys_to_pfn(S5PV310_PA_GPIO1),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO1),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO2,

		.pfn		= __phys_to_pfn(S5PV310_PA_GPIO2),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO3,

		.pfn		= __phys_to_pfn(S5PV310_PA_GPIO3),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO3),

		.length		= SZ_256,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_DMC0,

		.pfn		= __phys_to_pfn(S5PV310_PA_DMC0),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {
@@ -87,13 +87,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = { 
		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_SROMC,

		.pfn		= __phys_to_pfn(S5PV310_PA_SROMC),

		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	},

};



static void s5pv310_idle(void)

static void exynos4_idle(void)

{

	if (!need_resched())

		cpu_do_idle();
@@ -101,32 +101,33 @@ static void s5pv310_idle(void) 
	local_irq_enable();

}



/* s5pv310_map_io

/*

 * exynos4_map_io

 *

 * register the standard cpu IO areas

 */

void __init s5pv310_map_io(void)

void __init exynos4_map_io(void)

{

	iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));

	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));



	/* initialize device information early */

	s5pv310_default_sdhci0();

	s5pv310_default_sdhci1();

	s5pv310_default_sdhci2();

	s5pv310_default_sdhci3();

	exynos4_default_sdhci0();

	exynos4_default_sdhci1();

	exynos4_default_sdhci2();

	exynos4_default_sdhci3();

}



void __init s5pv310_init_clocks(int xtal)

void __init exynos4_init_clocks(int xtal)

{

	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);



	s3c24xx_register_baseclocks(xtal);

	s5p_register_clocks(xtal);

	s5pv310_register_clocks();

	s5pv310_setup_clocks();

	exynos4_register_clocks();

	exynos4_setup_clocks();

}



void __init s5pv310_init_irq(void)

void __init exynos4_init_irq(void)

{

	int irq;
@@ -148,29 +149,29 @@ void __init s5pv310_init_irq(void) 
	}



	/* The parameters of s5p_init_irq() are for VIC init.

	 * Theses parameters should be NULL and 0 because S5PV310

	 * Theses parameters should be NULL and 0 because EXYNOS4

	 * uses GIC instead of VIC.

	 */

	s5p_init_irq(NULL, 0);

}



struct sysdev_class s5pv310_sysclass = {

	.name	= "s5pv310-core",

struct sysdev_class exynos4_sysclass = {

	.name	= "exynos4-core",

};



static struct sys_device s5pv310_sysdev = {

	.cls	= &s5pv310_sysclass,

static struct sys_device exynos4_sysdev = {

	.cls	= &exynos4_sysclass,

};



static int __init s5pv310_core_init(void)

static int __init exynos4_core_init(void)

{

	return sysdev_class_register(&s5pv310_sysclass);

	return sysdev_class_register(&exynos4_sysclass);

}



core_initcall(s5pv310_core_init);

core_initcall(exynos4_core_init);



#ifdef CONFIG_CACHE_L2X0

static int __init s5pv310_l2x0_cache_init(void)

static int __init exynos4_l2x0_cache_init(void)

{

	/* TAG, Data Latency Control: 2cycle */

	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -188,15 +189,15 @@ static int __init s5pv310_l2x0_cache_init(void) 
	return 0;

}



early_initcall(s5pv310_l2x0_cache_init);

early_initcall(exynos4_l2x0_cache_init);

#endif



int __init s5pv310_init(void)

int __init exynos4_init(void)

{

	printk(KERN_INFO "S5PV310: Initializing architecture\n");

	printk(KERN_INFO "EXYNOS4: Initializing architecture\n");



	/* set idle function */

	pm_idle = s5pv310_idle;

	pm_idle = exynos4_idle;



	return sysdev_register(&s5pv310_sysdev);

	return sysdev_register(&exynos4_sysdev);

}

arch/arm/mach-s5pv310/cpufreq.c→arch/arm/mach-exynos4/cpufreq.c

+50 −50
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5pv310/cpufreq.c

/* linux/arch/arm/mach-exynos4/cpufreq.c

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * S5PV310 - CPU frequency scaling support

 * EXYNOS4 - CPU frequency scaling support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -39,7 +39,7 @@ static struct regulator *int_regulator; 
static struct cpufreq_freqs freqs;

static unsigned int memtype;



enum s5pv310_memory_type {

enum exynos4_memory_type {

	DDR2 = 4,

	LPDDR2,

	DDR3,
@@ -49,7 +49,7 @@ enum cpufreq_level_index { 
	L0, L1, L2, L3, CPUFREQ_LEVEL_END,

};



static struct cpufreq_frequency_table s5pv310_freq_table[] = {

static struct cpufreq_frequency_table exynos4_freq_table[] = {

	{L0, 1000*1000},

	{L1, 800*1000},

	{L2, 400*1000},
@@ -160,7 +160,7 @@ struct cpufreq_voltage_table { 
	unsigned int	int_volt;

};



static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {

static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {

	{

		.index		= L0,

		.arm_volt	= 1200000,
@@ -180,7 +180,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { 
	},

};



static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {

static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {

	/* APLL FOUT L0: 1000MHz */

	((250 << 16) | (6 << 8) | 1),
@@ -194,17 +194,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { 
	((200 << 16) | (6 << 8) | 4),

};



int s5pv310_verify_speed(struct cpufreq_policy *policy)

int exynos4_verify_speed(struct cpufreq_policy *policy)

{

	return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);

	return cpufreq_frequency_table_verify(policy, exynos4_freq_table);

}



unsigned int s5pv310_getspeed(unsigned int cpu)

unsigned int exynos4_getspeed(unsigned int cpu)

{

	return clk_get_rate(cpu_clk) / 1000;

}



void s5pv310_set_clkdiv(unsigned int div_index)

void exynos4_set_clkdiv(unsigned int div_index)

{

	unsigned int tmp;
@@ -321,7 +321,7 @@ void s5pv310_set_clkdiv(unsigned int div_index) 
	} while (tmp & 0x11);

}



static void s5pv310_set_apll(unsigned int index)

static void exynos4_set_apll(unsigned int index)

{

	unsigned int tmp;
@@ -340,7 +340,7 @@ static void s5pv310_set_apll(unsigned int index) 
	/* 3. Change PLL PMS values */

	tmp = __raw_readl(S5P_APLL_CON0);

	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));

	tmp |= s5pv310_apll_pms_table[index];

	tmp |= exynos4_apll_pms_table[index];

	__raw_writel(tmp, S5P_APLL_CON0);



	/* 4. wait_lock_time */
@@ -357,77 +357,77 @@ static void s5pv310_set_apll(unsigned int index) 
	} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));

}



static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)

static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)

{

	unsigned int tmp;



	if (old_index > new_index) {

		/* The frequency changing to L0 needs to change apll */

		if (freqs.new == s5pv310_freq_table[L0].frequency) {

		if (freqs.new == exynos4_freq_table[L0].frequency) {

			/* 1. Change the system clock divider values */

			s5pv310_set_clkdiv(new_index);

			exynos4_set_clkdiv(new_index);



			/* 2. Change the apll m,p,s value */

			s5pv310_set_apll(new_index);

			exynos4_set_apll(new_index);

		} else {

			/* 1. Change the system clock divider values */

			s5pv310_set_clkdiv(new_index);

			exynos4_set_clkdiv(new_index);



			/* 2. Change just s value in apll m,p,s value */

			tmp = __raw_readl(S5P_APLL_CON0);

			tmp &= ~(0x7 << 0);

			tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);

			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);

			__raw_writel(tmp, S5P_APLL_CON0);

		}

	}



	else if (old_index < new_index) {

		/* The frequency changing from L0 needs to change apll */

		if (freqs.old == s5pv310_freq_table[L0].frequency) {

		if (freqs.old == exynos4_freq_table[L0].frequency) {

			/* 1. Change the apll m,p,s value */

			s5pv310_set_apll(new_index);

			exynos4_set_apll(new_index);



			/* 2. Change the system clock divider values */

			s5pv310_set_clkdiv(new_index);

			exynos4_set_clkdiv(new_index);

		} else {

			/* 1. Change just s value in apll m,p,s value */

			tmp = __raw_readl(S5P_APLL_CON0);

			tmp &= ~(0x7 << 0);

			tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);

			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);

			__raw_writel(tmp, S5P_APLL_CON0);



			/* 2. Change the system clock divider values */

			s5pv310_set_clkdiv(new_index);

			exynos4_set_clkdiv(new_index);

		}

	}

}



static int s5pv310_target(struct cpufreq_policy *policy,

static int exynos4_target(struct cpufreq_policy *policy,

			  unsigned int target_freq,

			  unsigned int relation)

{

	unsigned int index, old_index;

	unsigned int arm_volt, int_volt;



	freqs.old = s5pv310_getspeed(policy->cpu);

	freqs.old = exynos4_getspeed(policy->cpu);



	if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,

					   freqs.old, relation, &old_index))

		return -EINVAL;



	if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,

					   target_freq, relation, &index))

		return -EINVAL;



	freqs.new = s5pv310_freq_table[index].frequency;

	freqs.new = exynos4_freq_table[index].frequency;

	freqs.cpu = policy->cpu;



	if (freqs.new == freqs.old)

		return 0;



	/* get the voltage value */

	arm_volt = s5pv310_volt_table[index].arm_volt;

	int_volt = s5pv310_volt_table[index].int_volt;

	arm_volt = exynos4_volt_table[index].arm_volt;

	int_volt = exynos4_volt_table[index].int_volt;



	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -441,7 +441,7 @@ static int s5pv310_target(struct cpufreq_policy *policy, 
	}



	/* Clock Configuration Procedure */

	s5pv310_set_frequency(old_index, index);

	exynos4_set_frequency(old_index, index);



	/* control regulator */

	if (freqs.new < freqs.old) {
@@ -458,52 +458,52 @@ static int s5pv310_target(struct cpufreq_policy *policy, 
}



#ifdef CONFIG_PM

static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,

static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,

				   pm_message_t pmsg)

{

	return 0;

}



static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)

static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)

{

	return 0;

}

#endif



static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)

static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)

{

	policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);

	policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);



	cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);

	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);



	/* set the transition latency value */

	policy->cpuinfo.transition_latency = 100000;



	/*

	 * S5PV310 multi-core processors has 2 cores

	 * EXYNOS4 multi-core processors has 2 cores

	 * that the frequency cannot be set independently.

	 * Each cpu is bound to the same speed.

	 * So the affected cpu is all of the cpus.

	 */

	cpumask_setall(policy->cpus);



	return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);

	return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);

}



static struct cpufreq_driver s5pv310_driver = {

static struct cpufreq_driver exynos4_driver = {

	.flags		= CPUFREQ_STICKY,

	.verify		= s5pv310_verify_speed,

	.target		= s5pv310_target,

	.get		= s5pv310_getspeed,

	.init		= s5pv310_cpufreq_cpu_init,

	.name		= "s5pv310_cpufreq",

	.verify		= exynos4_verify_speed,

	.target		= exynos4_target,

	.get		= exynos4_getspeed,

	.init		= exynos4_cpufreq_cpu_init,

	.name		= "exynos4_cpufreq",

#ifdef CONFIG_PM

	.suspend	= s5pv310_cpufreq_suspend,

	.resume		= s5pv310_cpufreq_resume,

	.suspend	= exynos4_cpufreq_suspend,

	.resume		= exynos4_cpufreq_resume,

#endif

};



static int __init s5pv310_cpufreq_init(void)

static int __init exynos4_cpufreq_init(void)

{

	cpu_clk = clk_get(NULL, "armclk");

	if (IS_ERR(cpu_clk))
@@ -550,7 +550,7 @@ static int __init s5pv310_cpufreq_init(void) 
		printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);

	}



	return cpufreq_register_driver(&s5pv310_driver);

	return cpufreq_register_driver(&exynos4_driver);



out:

	if (!IS_ERR(cpu_clk))
@@ -577,4 +577,4 @@ static int __init s5pv310_cpufreq_init(void) 


	return -EINVAL;

}

late_initcall(s5pv310_cpufreq_init);
 
late_initcall(exynos4_cpufreq_init);

arch/arm/mach-s5pv310/dma.c→arch/arm/mach-exynos4/dma.c

+27 −23
Original line number Diff line number Diff line 
/*

/* linux/arch/arm/mach-exynos4/dma.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * Copyright (C) 2010 Samsung Electronics Co. Ltd.

 *	Jaswinder Singh <jassi.brar@samsung.com>

 *
@@ -30,10 +34,10 @@ 


static u64 dma_dmamask = DMA_BIT_MASK(32);



static struct resource s5pv310_pdma0_resource[] = {

static struct resource exynos4_pdma0_resource[] = {

	[0] = {

		.start	= S5PV310_PA_PDMA0,

		.end	= S5PV310_PA_PDMA0 + SZ_4K,

		.start	= EXYNOS4_PA_PDMA0,

		.end	= EXYNOS4_PA_PDMA0 + SZ_4K,

		.flags	= IORESOURCE_MEM,

	},

	[1] = {
@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = { 
	},

};



static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {

static struct s3c_pl330_platdata exynos4_pdma0_pdata = {

	.peri = {

		[0] = DMACH_PCM0_RX,

		[1] = DMACH_PCM0_TX,
@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { 
	},

};



static struct platform_device s5pv310_device_pdma0 = {

static struct platform_device exynos4_device_pdma0 = {

	.name		= "s3c-pl330",

	.id		= 0,

	.num_resources	= ARRAY_SIZE(s5pv310_pdma0_resource),

	.resource	= s5pv310_pdma0_resource,

	.num_resources	= ARRAY_SIZE(exynos4_pdma0_resource),

	.resource	= exynos4_pdma0_resource,

	.dev		= {

		.dma_mask = &dma_dmamask,

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.platform_data = &s5pv310_pdma0_pdata,

		.platform_data = &exynos4_pdma0_pdata,

	},

};



static struct resource s5pv310_pdma1_resource[] = {

static struct resource exynos4_pdma1_resource[] = {

	[0] = {

		.start	= S5PV310_PA_PDMA1,

		.end	= S5PV310_PA_PDMA1 + SZ_4K,

		.start	= EXYNOS4_PA_PDMA1,

		.end	= EXYNOS4_PA_PDMA1 + SZ_4K,

		.flags	= IORESOURCE_MEM,

	},

	[1] = {
@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = { 
	},

};



static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {

static struct s3c_pl330_platdata exynos4_pdma1_pdata = {

	.peri = {

		[0] = DMACH_PCM0_RX,

		[1] = DMACH_PCM0_TX,
@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { 
	},

};



static struct platform_device s5pv310_device_pdma1 = {

static struct platform_device exynos4_device_pdma1 = {

	.name		= "s3c-pl330",

	.id		= 1,

	.num_resources	= ARRAY_SIZE(s5pv310_pdma1_resource),

	.resource	= s5pv310_pdma1_resource,

	.num_resources	= ARRAY_SIZE(exynos4_pdma1_resource),

	.resource	= exynos4_pdma1_resource,

	.dev		= {

		.dma_mask = &dma_dmamask,

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.platform_data = &s5pv310_pdma1_pdata,

		.platform_data = &exynos4_pdma1_pdata,

	},

};



static struct platform_device *s5pv310_dmacs[] __initdata = {

	&s5pv310_device_pdma0,

	&s5pv310_device_pdma1,

static struct platform_device *exynos4_dmacs[] __initdata = {

	&exynos4_device_pdma0,

	&exynos4_device_pdma1,

};



static int __init s5pv310_dma_init(void)

static int __init exynos4_dma_init(void)

{

	platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));

	platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));



	return 0;

}

arch_initcall(s5pv310_dma_init);
 
arch_initcall(exynos4_dma_init);

arch/arm/mach-s5pv310/gpiolib.c→arch/arm/mach-exynos4/gpiolib.c

+77 −77
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5pv310/gpiolib.c

/* linux/arch/arm/mach-exynos4/gpiolib.c

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * S5PV310 - GPIOlib support

 * EXYNOS4 - GPIOlib support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -43,159 +43,159 @@ static struct s3c_gpio_cfg gpio_cfg_noint = { 
 * Note: The initialization of 'base' member of s3c_gpio_chip structure

 * uses the above macro and depends on the banks being listed in order here.

 */

static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {

static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {

	{

		.chip	= {

			.base	= S5PV310_GPA0(0),

			.ngpio	= S5PV310_GPIO_A0_NR,

			.base	= EXYNOS4_GPA0(0),

			.ngpio	= EXYNOS4_GPIO_A0_NR,

			.label	= "GPA0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPA1(0),

			.ngpio	= S5PV310_GPIO_A1_NR,

			.base	= EXYNOS4_GPA1(0),

			.ngpio	= EXYNOS4_GPIO_A1_NR,

			.label	= "GPA1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPB(0),

			.ngpio	= S5PV310_GPIO_B_NR,

			.base	= EXYNOS4_GPB(0),

			.ngpio	= EXYNOS4_GPIO_B_NR,

			.label	= "GPB",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPC0(0),

			.ngpio	= S5PV310_GPIO_C0_NR,

			.base	= EXYNOS4_GPC0(0),

			.ngpio	= EXYNOS4_GPIO_C0_NR,

			.label	= "GPC0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPC1(0),

			.ngpio	= S5PV310_GPIO_C1_NR,

			.base	= EXYNOS4_GPC1(0),

			.ngpio	= EXYNOS4_GPIO_C1_NR,

			.label	= "GPC1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPD0(0),

			.ngpio	= S5PV310_GPIO_D0_NR,

			.base	= EXYNOS4_GPD0(0),

			.ngpio	= EXYNOS4_GPIO_D0_NR,

			.label	= "GPD0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPD1(0),

			.ngpio	= S5PV310_GPIO_D1_NR,

			.base	= EXYNOS4_GPD1(0),

			.ngpio	= EXYNOS4_GPIO_D1_NR,

			.label	= "GPD1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPE0(0),

			.ngpio	= S5PV310_GPIO_E0_NR,

			.base	= EXYNOS4_GPE0(0),

			.ngpio	= EXYNOS4_GPIO_E0_NR,

			.label	= "GPE0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPE1(0),

			.ngpio	= S5PV310_GPIO_E1_NR,

			.base	= EXYNOS4_GPE1(0),

			.ngpio	= EXYNOS4_GPIO_E1_NR,

			.label	= "GPE1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPE2(0),

			.ngpio	= S5PV310_GPIO_E2_NR,

			.base	= EXYNOS4_GPE2(0),

			.ngpio	= EXYNOS4_GPIO_E2_NR,

			.label	= "GPE2",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPE3(0),

			.ngpio	= S5PV310_GPIO_E3_NR,

			.base	= EXYNOS4_GPE3(0),

			.ngpio	= EXYNOS4_GPIO_E3_NR,

			.label	= "GPE3",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPE4(0),

			.ngpio	= S5PV310_GPIO_E4_NR,

			.base	= EXYNOS4_GPE4(0),

			.ngpio	= EXYNOS4_GPIO_E4_NR,

			.label	= "GPE4",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPF0(0),

			.ngpio	= S5PV310_GPIO_F0_NR,

			.base	= EXYNOS4_GPF0(0),

			.ngpio	= EXYNOS4_GPIO_F0_NR,

			.label	= "GPF0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPF1(0),

			.ngpio	= S5PV310_GPIO_F1_NR,

			.base	= EXYNOS4_GPF1(0),

			.ngpio	= EXYNOS4_GPIO_F1_NR,

			.label	= "GPF1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPF2(0),

			.ngpio	= S5PV310_GPIO_F2_NR,

			.base	= EXYNOS4_GPF2(0),

			.ngpio	= EXYNOS4_GPIO_F2_NR,

			.label	= "GPF2",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPF3(0),

			.ngpio	= S5PV310_GPIO_F3_NR,

			.base	= EXYNOS4_GPF3(0),

			.ngpio	= EXYNOS4_GPIO_F3_NR,

			.label	= "GPF3",

		},

	},

};



static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {

static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {

	{

		.chip	= {

			.base	= S5PV310_GPJ0(0),

			.ngpio	= S5PV310_GPIO_J0_NR,

			.base	= EXYNOS4_GPJ0(0),

			.ngpio	= EXYNOS4_GPIO_J0_NR,

			.label	= "GPJ0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPJ1(0),

			.ngpio	= S5PV310_GPIO_J1_NR,

			.base	= EXYNOS4_GPJ1(0),

			.ngpio	= EXYNOS4_GPIO_J1_NR,

			.label	= "GPJ1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPK0(0),

			.ngpio	= S5PV310_GPIO_K0_NR,

			.base	= EXYNOS4_GPK0(0),

			.ngpio	= EXYNOS4_GPIO_K0_NR,

			.label	= "GPK0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPK1(0),

			.ngpio	= S5PV310_GPIO_K1_NR,

			.base	= EXYNOS4_GPK1(0),

			.ngpio	= EXYNOS4_GPIO_K1_NR,

			.label	= "GPK1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPK2(0),

			.ngpio	= S5PV310_GPIO_K2_NR,

			.base	= EXYNOS4_GPK2(0),

			.ngpio	= EXYNOS4_GPIO_K2_NR,

			.label	= "GPK2",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPK3(0),

			.ngpio	= S5PV310_GPIO_K3_NR,

			.base	= EXYNOS4_GPK3(0),

			.ngpio	= EXYNOS4_GPIO_K3_NR,

			.label	= "GPK3",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPL0(0),

			.ngpio	= S5PV310_GPIO_L0_NR,

			.base	= EXYNOS4_GPL0(0),

			.ngpio	= EXYNOS4_GPIO_L0_NR,

			.label	= "GPL0",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPL1(0),

			.ngpio	= S5PV310_GPIO_L1_NR,

			.base	= EXYNOS4_GPL1(0),

			.ngpio	= EXYNOS4_GPIO_L1_NR,

			.label	= "GPL1",

		},

	}, {

		.chip	= {

			.base	= S5PV310_GPL2(0),

			.ngpio	= S5PV310_GPIO_L2_NR,

			.base	= EXYNOS4_GPL2(0),

			.ngpio	= EXYNOS4_GPIO_L2_NR,

			.label	= "GPL2",

		},

	}, {
@@ -203,8 +203,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 
		.config	= &gpio_cfg_noint,

		.irq_base = IRQ_EINT(0),

		.chip	= {

			.base	= S5PV310_GPX0(0),

			.ngpio	= S5PV310_GPIO_X0_NR,

			.base	= EXYNOS4_GPX0(0),

			.ngpio	= EXYNOS4_GPIO_X0_NR,

			.label	= "GPX0",

			.to_irq	= samsung_gpiolib_to_irq,

		},
@@ -213,8 +213,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 
		.config	= &gpio_cfg_noint,

		.irq_base = IRQ_EINT(8),

		.chip	= {

			.base	= S5PV310_GPX1(0),

			.ngpio	= S5PV310_GPIO_X1_NR,

			.base	= EXYNOS4_GPX1(0),

			.ngpio	= EXYNOS4_GPIO_X1_NR,

			.label	= "GPX1",

			.to_irq	= samsung_gpiolib_to_irq,

		},
@@ -223,8 +223,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 
		.config	= &gpio_cfg_noint,

		.irq_base = IRQ_EINT(16),

		.chip	= {

			.base	= S5PV310_GPX2(0),

			.ngpio	= S5PV310_GPIO_X2_NR,

			.base	= EXYNOS4_GPX2(0),

			.ngpio	= EXYNOS4_GPIO_X2_NR,

			.label	= "GPX2",

			.to_irq	= samsung_gpiolib_to_irq,

		},
@@ -233,25 +233,25 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 
		.config	= &gpio_cfg_noint,

		.irq_base = IRQ_EINT(24),

		.chip	= {

			.base	= S5PV310_GPX3(0),

			.ngpio	= S5PV310_GPIO_X3_NR,

			.base	= EXYNOS4_GPX3(0),

			.ngpio	= EXYNOS4_GPIO_X3_NR,

			.label	= "GPX3",

			.to_irq	= samsung_gpiolib_to_irq,

		},

	},

};



static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {

static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {

	{

		.chip	= {

			.base	= S5PV310_GPZ(0),

			.ngpio	= S5PV310_GPIO_Z_NR,

			.base	= EXYNOS4_GPZ(0),

			.ngpio	= EXYNOS4_GPIO_Z_NR,

			.label	= "GPZ",

		},

	},

};



static __init int s5pv310_gpiolib_init(void)

static __init int exynos4_gpiolib_init(void)

{

	struct s3c_gpio_chip *chip;

	int i;
@@ -259,8 +259,8 @@ static __init int s5pv310_gpiolib_init(void) 


	/* GPIO part 1 */



	chip = s5pv310_gpio_part1_4bit;

	nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);

	chip = exynos4_gpio_part1_4bit;

	nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);



	for (i = 0; i < nr_chips; i++, chip++) {

		if (chip->config == NULL)
@@ -269,12 +269,12 @@ static __init int s5pv310_gpiolib_init(void) 
			chip->base = S5P_VA_GPIO1 + (i) * 0x20;

	}



	samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);

	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);



	/* GPIO part 2 */



	chip = s5pv310_gpio_part2_4bit;

	nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);

	chip = exynos4_gpio_part2_4bit;

	nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);



	for (i = 0; i < nr_chips; i++, chip++) {

		if (chip->config == NULL)
@@ -283,12 +283,12 @@ static __init int s5pv310_gpiolib_init(void) 
			chip->base = S5P_VA_GPIO2 + (i) * 0x20;

	}



	samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);

	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);



	/* GPIO part 3 */



	chip = s5pv310_gpio_part3_4bit;

	nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);

	chip = exynos4_gpio_part3_4bit;

	nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);



	for (i = 0; i < nr_chips; i++, chip++) {

		if (chip->config == NULL)
@@ -297,8 +297,8 @@ static __init int s5pv310_gpiolib_init(void) 
			chip->base = S5P_VA_GPIO3 + (i) * 0x20;

	}



	samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);

	samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);



	return 0;

}

core_initcall(s5pv310_gpiolib_init);
 
core_initcall(exynos4_gpiolib_init);

arch/arm/mach-s5pv310/headsmp.S→arch/arm/mach-exynos4/headsmp.S

+3 −3
Original line number Diff line number Diff line 
/*

 *  linux/arch/arm/mach-s5pv310/headsmp.S

 *  linux/arch/arm/mach-exynos4/headsmp.S

 *

 *  Cloned from linux/arch/arm/mach-realview/headsmp.S

 *
@@ -16,11 +16,11 @@ 
	__INIT



/*

 * s5pv310 specific entry point for secondary CPUs.  This provides

 * exynos4 specific entry point for secondary CPUs.  This provides

 * a "holding pen" into which all secondary cores are held until we're

 * ready for them to initialise.

 */

ENTRY(s5pv310_secondary_startup)

ENTRY(exynos4_secondary_startup)

	mrc	p15, 0, r0, c0, c0, 5

	and	r0, r0, #15

	adr	r4, 1f