MIPS: MSP71xx: Use __flush_cache_all instead of flush_cache_all.



Flushing caches is probably sensible on reset but flush_cache_all has been
a no-op for a very long time.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 9329c154

arch/mips/pmcs-msp71xx/msp_setup.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -118,7 +118,7 @@ void msp_restart(char *command)
		/* No chip-specific reset code, just jump to the ROM reset vector */
		set_c0_status(ST0_BEV \| ST0_ERL);
		change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
		flush_cache_all();
		__flush_cache_all();
		write_c0_wired(0);

		__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));