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Commit 7c289385 authored by Russell King's avatar Russell King
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ALSA: AACI: allow writes to MAINCR to take effect 



The AACI TRM requires the MAINCR enable bit to be held zero for two
bitclk cycles plus three apb_pclk cycles.  Use a delay of 1us to
ensure this.

Ensure that writes to MAINCR to change the addressed codec only happen
when required, and that they take effect in a similar manner to the
above, otherwise we seem to occasionally have stuck slot busy bits.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ec11594f

sound/arm/aaci.c

+7 −1
Original line number Diff line number Diff line
@@ -50,7 +50,11 @@ static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) 
	if (v & SLFR_1RXV)

		readl(aaci->base + AACI_SL1RX);



	if (maincr != readl(aaci->base + AACI_MAINCR)) {

		writel(maincr, aaci->base + AACI_MAINCR);

		readl(aaci->base + AACI_MAINCR);

		udelay(1);

	}

}



/*
@@ -993,6 +997,8 @@ static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) 
	 * disabling the channel doesn't clear the FIFO.

	 */

	writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);

	readl(aaci->base + AACI_MAINCR);

	udelay(1);

	writel(aaci->maincr, aaci->base + AACI_MAINCR);



	/*