Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7be1f6b9 authored by Stefan Roese's avatar Stefan Roese Committed by David Woodhouse
Browse files

mtd: cfi_cmdset_0001: Fix problem with unlocking timeout



Unlocking may take up to 1.4 seconds on some Intel flashes. So
lets use a max. of 1.5 seconds (1500ms) as timeout.

See "Clear Block Lock-Bits Time" on page 40 in
"3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
from February 2003

This patch also fixes some other problems with this timeout:

- Don't use HZ in timeout "calculation"!
  While testing we noticed that an unlocking timeout occured with
  HZ=1000 and didn't occur with HZ=300. This was because the
  timeout parameter was calculated differently depending on the
  HZ value. Now a fixed value of 1500ms is used.

- The last parameter of WAIT_TIMEOUT (defined to
  inval_cache_and_wait_for_operation) has to be passed in
  micro-seconds. So multiply the ms value with 1000 and not 100
  to calculate this value.

- Use variable name "mdelay" instead of misleading "udelay".

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Tested-by: default avatarStephan Gatzka <stephan@gatzka.org>
Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent a5ff4f10
Loading
Loading
Loading
Loading
+11 −3
Original line number Diff line number Diff line
@@ -2043,7 +2043,7 @@ static int __xipram do_xxlock_oneblock(struct map_info *map, struct flchip *chip
{
	struct cfi_private *cfi = map->fldrv_priv;
	struct cfi_pri_intelext *extp = cfi->cmdset_priv;
	int udelay;
	int mdelay;
	int ret;

	adr += chip->start;
@@ -2072,9 +2072,17 @@ static int __xipram do_xxlock_oneblock(struct map_info *map, struct flchip *chip
	 * If Instant Individual Block Locking supported then no need
	 * to delay.
	 */
	udelay = (!extp || !(extp->FeatureSupport & (1 << 5))) ? 1000000/HZ : 0;
	/*
	 * Unlocking may take up to 1.4 seconds on some Intel flashes. So
	 * lets use a max of 1.5 seconds (1500ms) as timeout.
	 *
	 * See "Clear Block Lock-Bits Time" on page 40 in
	 * "3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
	 * from February 2003
	 */
	mdelay = (!extp || !(extp->FeatureSupport & (1 << 5))) ? 1500 : 0;

	ret = WAIT_TIMEOUT(map, chip, adr, udelay, udelay * 100);
	ret = WAIT_TIMEOUT(map, chip, adr, mdelay, mdelay * 1000);
	if (ret) {
		map_write(map, CMD(0x70), adr);
		chip->state = FL_STATUS;