Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7aed17f4 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman
Browse files

ARM: dts: r8a7793: Add I2C master nodes to DT 



Instantiate all the 9 I2C controllers in the disabled state.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c5af8a42

arch/arm/boot/dts/r8a7793.dtsi

+132 −3
Original line number Diff line number Diff line
@@ -19,6 +19,15 @@ 
	#size-cells = <2>;



	aliases {

		i2c0 = &i2c0;

		i2c1 = &i2c1;

		i2c2 = &i2c2;

		i2c3 = &i2c3;

		i2c4 = &i2c4;

		i2c5 = &i2c5;

		i2c6 = &i2c6;

		i2c7 = &i2c7;

		i2c8 = &i2c8;

		spi0 = &qspi;

	};
@@ -230,6 +239,120 @@ 
		power-domains = <&cpg_clocks>;

	};



	/* The memory map in the User's Manual maps the cores to bus numbers */

	i2c0: i2c@e6508000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6508000 0 0x40>;

		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C0>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <6>;

		status = "disabled";

	};



	i2c1: i2c@e6518000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6518000 0 0x40>;

		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C1>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <6>;

		status = "disabled";

	};



	i2c2: i2c@e6530000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6530000 0 0x40>;

		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C2>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <6>;

		status = "disabled";

	};



	i2c3: i2c@e6540000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6540000 0 0x40>;

		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C3>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <6>;

		status = "disabled";

	};



	i2c4: i2c@e6520000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6520000 0 0x40>;

		interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C4>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <6>;

		status = "disabled";

	};



	i2c5: i2c@e6528000 {

		/* doesn't need pinmux */

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,i2c-r8a7793";

		reg = <0 0xe6528000 0 0x40>;

		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_I2C5>;

		power-domains = <&cpg_clocks>;

		i2c-scl-internal-delay-ns = <110>;

		status = "disabled";

	};



	i2c6: i2c@e60b0000 {

		/* doesn't need pinmux */

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";

		reg = <0 0xe60b0000 0 0x425>;

		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;

		dmas = <&dmac0 0x77>, <&dmac0 0x78>;

		dma-names = "tx", "rx";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	i2c7: i2c@e6500000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";

		reg = <0 0xe6500000 0 0x425>;

		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7793_CLK_IIC0>;

		dmas = <&dmac0 0x61>, <&dmac0 0x62>;

		dma-names = "tx", "rx";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	i2c8: i2c@e6510000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";

		reg = <0 0xe6510000 0 0x425>;

		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7793_CLK_IIC1>;

		dmas = <&dmac0 0x65>, <&dmac0 0x66>;

		dma-names = "tx", "rx";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	pfc: pfc@e6060000 {

		compatible = "renesas,pfc-r8a7793";

		reg = <0 0xe6060000 0 0x250>;
@@ -820,19 +943,25 @@ 
			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;

			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,

				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,

				 <&cpg_clocks R8A7793_CLK_QSPI>;

				 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,

				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,

				 <&hp_clk>, <&hp_clk>;

			#clock-cells = <1>;

			clock-indices = <

				R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6

				R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4

				R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2

				R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0

				R8A7793_CLK_QSPI_MOD

				R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5

				R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4

				R8A7793_CLK_I2C3 R8A7793_CLK_I2C2

				R8A7793_CLK_I2C1 R8A7793_CLK_I2C0

			>;

			clock-output-names =

				"gpio7", "gpio6", "gpio5", "gpio4",

				"gpio3", "gpio2", "gpio1", "gpio0",

				"qspi_mod";

				"qspi_mod", "i2c5", "i2c6", "i2c4",

				"i2c3", "i2c2", "i2c1", "i2c0";

		};

		mstp11_clks: mstp11_clks@e615099c {

			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";