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Commit 7abd42ea authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux 

Pull clk framework fixes from Mike Turquette:
 "Clock framework and driver fixes, all of which fix user-visible
  regressions.

  There is a single framework fix that prevents dereferencing a NULL
  pointer when calling clk_get.  The range of fixes for clock driver
  regressions spans memory leak fixes, touching the wrong registers that
  cause things to explode, misconfigured clock rates that result in
  non-responsive devices and even some boot failures.  The most benign
  fix is DT binding doc typo.  It is a stable ABI exposed from the
  kernel that was introduced in -rc1, so best to fix it now"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
  clk:at91: Fix memory leak in of_at91_clk_master_setup()
  clk: nomadik: fix multiplatform problem
  clk: Correct handling of NULL clk in __clk_{get, put}
  clk: shmobile: Fix typo in MSTP clock DT bindings
  clk: shmobile: rcar-gen2: Fix qspi divisor
  clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocks
  clk: tegra124: remove gr2d and gr3d clocks
  clk: tegra: Fix vic03 mux index
  clk: shmobile: rcar-gen2: Fix qspi divisor
  clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
  clk: tegra: use max divider if divider overflows
  clk: tegra: cclk_lp has a pllx/2 divider
  clk: tegra: fix sdmmc clks on Tegra1x4
  clk: tegra: fix host1x clock on Tegra124
  clk: tegra: PLLD2 fixes for hdmi
  clk: tegra: Fix PLLD mnp table
  clk: tegra: Fix PLLP rate table
  clk: tegra: Correct clock number for UARTE
  clk: tegra: Add missing Tegra20 fuse clks
  ARM: keystone: dts: fix clkvcp3 control register address
  ...
parents 0414855f f63fcc90

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

+2 −2
Original line number Diff line number Diff line
@@ -21,9 +21,9 @@ Required Properties: 
    must appear in the same order as the output clocks.

  - #clock-cells: Must be 1

  - clock-output-names: The name of the clocks as free-form strings

  - renesas,indices: Indices of the gate clocks into the group (0 to 31)

  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)



The clocks, clock-output-names and renesas,indices properties contain one

The clocks, clock-output-names and renesas,clock-indices properties contain one

entry per gate clock. The MSTP groups are sparsely populated. Unimplemented

gate clocks must not be declared.

arch/arm/boot/dts/keystone-clocks.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -612,7 +612,7 @@ clocks { 
		compatible = "ti,keystone,psc-clock";

		clocks = <&chipclk13>;

		clock-output-names = "vcp-3";

		reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;

		reg = <0x023500a8 0xb00>, <0x02350060 0x400>;

		reg-names = "control", "domain";

		domain-id = <24>;

	};

drivers/clk/at91/clk-master.c

+1 −1
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, 


	irq = irq_of_parse_and_map(np, 0);

	if (!irq)

		return;

		goto out_free_characteristics;



	clk = at91_clk_register_master(pmc, irq, name, num_parents,

				       parent_names, layout,

drivers/clk/clk-nomadik.c

+3 −0
Original line number Diff line number Diff line
@@ -494,6 +494,9 @@ static const struct file_operations nomadik_src_clk_debugfs_ops = { 


static int __init nomadik_src_clk_init_debugfs(void)

{

	/* Vital for multiplatform */

	if (!src_base)

		return -ENODEV;

	src_pcksr0_boot = readl(src_base + SRC_PCKSR0);

	src_pcksr1_boot = readl(src_base + SRC_PCKSR1);

	debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,

drivers/clk/clk.c

+7 −6
Original line number Diff line number Diff line
@@ -2226,23 +2226,24 @@ EXPORT_SYMBOL_GPL(devm_clk_unregister); 
 */

int __clk_get(struct clk *clk)

{

	if (clk && !try_module_get(clk->owner))

	if (clk) {

		if (!try_module_get(clk->owner))

			return 0;



		kref_get(&clk->ref);

	}

	return 1;

}



void __clk_put(struct clk *clk)

{

	if (WARN_ON_ONCE(IS_ERR(clk)))

	if (!clk || WARN_ON_ONCE(IS_ERR(clk)))

		return;



	clk_prepare_lock();

	kref_put(&clk->ref, __clk_release);

	clk_prepare_unlock();



	if (clk)

	module_put(clk->owner);

}