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Commit 78761147 authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge tag 'clk-hisi' of... 

Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon

updating clock drivers for Hisilicon
parents 9ce71ca1 75af25f5

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 
obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o

obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/

obj-$(CONFIG_ARCH_HI3xxx)		+= hisilicon/

obj-$(CONFIG_ARCH_HIP04)		+= hisilicon/

obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/

ifeq ($(CONFIG_COMMON_CLK), y)

obj-$(CONFIG_ARCH_MMP)			+= mmp/

drivers/clk/hisilicon/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -2,4 +2,7 @@ 
# Hisilicon Clock specific Makefile

#



obj-y	+= clk.o clkgate-separated.o clk-hi3620.o
 
obj-y	+= clk.o clkgate-separated.o



obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o

obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o

drivers/clk/hisilicon/clk-hi3620.c

+8 −17
Original line number Diff line number Diff line
@@ -210,34 +210,25 @@ static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = { 


static void __init hi3620_clk_init(struct device_node *np)

{

	void __iomem *base;

	struct hisi_clock_data *clk_data;



	if (np) {

		base = of_iomap(np, 0);

		if (!base) {

			pr_err("failed to map Hi3620 clock registers\n");

	clk_data = hisi_clk_init(np, HI3620_NR_CLKS);

	if (!clk_data)

		return;

		}

	} else {

		pr_err("failed to find Hi3620 clock node in DTS\n");

		return;

	}



	hisi_clk_init(np, HI3620_NR_CLKS);



	hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,

				     ARRAY_SIZE(hi3620_fixed_rate_clks),

				     base);

				     clk_data);

	hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,

				       ARRAY_SIZE(hi3620_fixed_factor_clks),

				       base);

				       clk_data);

	hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),

			      base);

			      clk_data);

	hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),

				  base);

				  clk_data);

	hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,

				   ARRAY_SIZE(hi3620_seperated_gate_clks),

				   base);

				   clk_data);

}

CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);

drivers/clk/hisilicon/clk-hip04.c

0 → 100644
+58 −0
Original line number Diff line number Diff line 
/*

 * Hisilicon HiP04 clock driver

 *

 * Copyright (c) 2013-2014 Hisilicon Limited.

 * Copyright (c) 2013-2014 Linaro Limited.

 *

 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License along

 * with this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 */



#include <linux/kernel.h>

#include <linux/clk-provider.h>

#include <linux/clkdev.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/slab.h>

#include <linux/clk.h>



#include <dt-bindings/clock/hip04-clock.h>



#include "clk.h"



/* fixed rate clocks */

static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {

	{ HIP04_OSC50M,   "osc50m",   NULL, CLK_IS_ROOT, 50000000, },

	{ HIP04_CLK_50M,  "clk50m",   NULL, CLK_IS_ROOT, 50000000, },

	{ HIP04_CLK_168M, "clk168m",  NULL, CLK_IS_ROOT, 168750000, },

};



static void __init hip04_clk_init(struct device_node *np)

{

	struct hisi_clock_data *clk_data;



	clk_data = hisi_clk_init(np, HIP04_NR_CLKS);

	if (!clk_data)

		return;



	hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,

				     ARRAY_SIZE(hip04_fixed_rate_clks),

				     clk_data);

}

CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);

drivers/clk/hisilicon/clk.c

+47 −15
Original line number Diff line number Diff line
@@ -37,23 +37,49 @@ 
#include "clk.h"



static DEFINE_SPINLOCK(hisi_clk_lock);

static struct clk **clk_table;

static struct clk_onecell_data clk_data;



void __init hisi_clk_init(struct device_node *np, int nr_clks)

struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,

					     int nr_clks)

{

	struct hisi_clock_data *clk_data;

	struct clk **clk_table;

	void __iomem *base;



	if (np) {

		base = of_iomap(np, 0);

		if (!base) {

			pr_err("failed to map Hisilicon clock registers\n");

			goto err;

		}

	} else {

		pr_err("failed to find Hisilicon clock node in DTS\n");

		goto err;

	}



	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);

	if (!clk_data) {

		pr_err("%s: could not allocate clock data\n", __func__);

		goto err;

	}

	clk_data->base = base;



	clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);

	if (!clk_table) {

		pr_err("%s: could not allocate clock lookup table\n", __func__);

		return;

		goto err_data;

	}

	clk_data.clks = clk_table;

	clk_data.clk_num = nr_clks;

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	clk_data->clk_data.clks = clk_table;

	clk_data->clk_data.clk_num = nr_clks;

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);

	return clk_data;

err_data:

	kfree(clk_data);

err:

	return NULL;

}



void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,

					 int nums, void __iomem *base)

					 int nums, struct hisi_clock_data *data)

{

	struct clk *clk;

	int i;
@@ -68,11 +94,13 @@ void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, 
			       __func__, clks[i].name);

			continue;

		}

		data->clk_data.clks[clks[i].id] = clk;

	}

}



void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,

					   int nums, void __iomem *base)

					   int nums,

					   struct hisi_clock_data *data)

{

	struct clk *clk;

	int i;
@@ -87,13 +115,15 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, 
			       __func__, clks[i].name);

			continue;

		}

		data->clk_data.clks[clks[i].id] = clk;

	}

}



void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,

				  int nums, void __iomem *base)

				  int nums, struct hisi_clock_data *data)

{

	struct clk *clk;

	void __iomem *base = data->base;

	int i;



	for (i = 0; i < nums; i++) {
@@ -111,14 +141,15 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, 
		if (clks[i].alias)

			clk_register_clkdev(clk, clks[i].alias, NULL);



		clk_table[clks[i].id] = clk;

		data->clk_data.clks[clks[i].id] = clk;

	}

}



void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,

				      int nums, void __iomem *base)

				      int nums, struct hisi_clock_data *data)

{

	struct clk *clk;

	void __iomem *base = data->base;

	int i;



	for (i = 0; i < nums; i++) {
@@ -139,14 +170,15 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, 
		if (clks[i].alias)

			clk_register_clkdev(clk, clks[i].alias, NULL);



		clk_table[clks[i].id] = clk;

		data->clk_data.clks[clks[i].id] = clk;

	}

}



void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,

				       int nums, void __iomem *base)

				       int nums, struct hisi_clock_data *data)

{

	struct clk *clk;

	void __iomem *base = data->base;

	int i;



	for (i = 0; i < nums; i++) {
@@ -166,6 +198,6 @@ void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, 
		if (clks[i].alias)

			clk_register_clkdev(clk, clks[i].alias, NULL);



		clk_table[clks[i].id] = clk;

		data->clk_data.clks[clks[i].id] = clk;

	}

}