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Commit 77f3ee59 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Markos Chandras
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MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction 



MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the
EHB instruction is available or not. This is necessary for MIPS R6
which also supports the EHB instruction.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent d2e6d30a

arch/mips/mm/tlbex.c

+3 −3
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, 
	case tlb_indexed: tlbw = uasm_i_tlbwi; break;

	}



	if (cpu_has_mips_r2) {

	if (cpu_has_mips_r2_exec_hazard) {

		/*

		 * The architecture spec says an ehb is required here,

		 * but a number of cores do not have the hazard and
@@ -1953,7 +1953,7 @@ static void build_r4000_tlb_load_handler(void) 


		switch (current_cpu_type()) {

		default:

			if (cpu_has_mips_r2) {

			if (cpu_has_mips_r2_exec_hazard) {

				uasm_i_ehb(&p);



		case CPU_CAVIUM_OCTEON:
@@ -2020,7 +2020,7 @@ static void build_r4000_tlb_load_handler(void) 


		switch (current_cpu_type()) {

		default:

			if (cpu_has_mips_r2) {

			if (cpu_has_mips_r2_exec_hazard) {

				uasm_i_ehb(&p);



		case CPU_CAVIUM_OCTEON: