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Commit 773328da authored by Felipe Balbi's avatar Felipe Balbi Committed by Lee Jones
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mfd: tps65218: Make INT[12] and STATUS registers volatile 



STATUS register can be modified by the HW, so we
should bypass cache because of that.

In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time they
are read. If we rely on the cache for them, we will
never be able to clear the interrupt, which will cause
our IRQ line to be disabled due to IRQ throttling.

Fixes: 44b4dc61 mfd: tps65218: Add driver for the TPS65218 PMIC
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent b3f6c73d

drivers/mfd/tps65218.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -125,10 +125,21 @@ int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, 
}

}

EXPORT_SYMBOL_GPL(tps65218_clear_bits);

EXPORT_SYMBOL_GPL(tps65218_clear_bits);





static const struct regmap_range tps65218_yes_ranges[] = {

	regmap_reg_range(TPS65218_REG_INT1, TPS65218_REG_INT2),

	regmap_reg_range(TPS65218_REG_STATUS, TPS65218_REG_STATUS),

};



static const struct regmap_access_table tps65218_volatile_table = {

	.yes_ranges = tps65218_yes_ranges,

	.n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),

};



static struct regmap_config tps65218_regmap_config = {

static struct regmap_config tps65218_regmap_config = {

	.reg_bits = 8,

	.reg_bits = 8,

	.val_bits = 8,

	.val_bits = 8,

	.cache_type = REGCACHE_RBTREE,

	.cache_type = REGCACHE_RBTREE,

	.volatile_table = &tps65218_volatile_table,

};

};





static const struct regmap_irq tps65218_irqs[] = {

static const struct regmap_irq tps65218_irqs[] = {