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Commit 76f8421f authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Perform Sandybridge BSD tail write under the forcewake 



Since we have a sequence of register reads and writes, we can reduce the
latency of starting the BSD ring by performing all the mmio operations
under the same forcewake wakeref.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467297225-21379-62-git-send-email-chris@chris-wilson.co.uk
parent 87273b71

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -3882,6 +3882,7 @@ __raw_write(64, q) 
 */

#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))

#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))

#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))

#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)



/* "Broadcast RGB" property */

drivers/gpu/drm/i915/intel_ringbuffer.c

+16 −12
Original line number Diff line number Diff line
@@ -2684,19 +2684,21 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, 
{

	struct drm_i915_private *dev_priv = engine->i915;



	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



       /* Every tail move must follow the sequence below */



	/* Disable notification that the ring is IDLE. The GT

	 * will then assume that it is busy and bring it out of rc6.

	 */

	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,

	I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,

		      _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));



	/* Clear the context id. Here be magic! */

	I915_WRITE64(GEN6_BSD_RNCID, 0x0);

	I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);



	/* Wait for the ring not to be idle, i.e. for it to wake up. */

	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register_fw(dev_priv,

				       GEN6_BSD_SLEEP_PSMI_CONTROL,

				       GEN6_BSD_SLEEP_INDICATOR,

				       0,
@@ -2704,14 +2706,16 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, 
		DRM_ERROR("timed out waiting for the BSD ring to wake up\n");



	/* Now that the ring is fully powered up, update the tail */

	I915_WRITE_TAIL(engine, value);

	POSTING_READ(RING_TAIL(engine->mmio_base));

	I915_WRITE_FW(RING_TAIL(engine->mmio_base), value);

	POSTING_READ_FW(RING_TAIL(engine->mmio_base));



	/* Let the ring send IDLE messages to the GT again,

	 * and so let it sleep to conserve power when idle.

	 */

	I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,

	I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,

		      _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,