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Commit 76ebc134 authored by Peter De Schrijver's avatar Peter De Schrijver
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clk: tegra: move periph clocks to common file



Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 6609dbe4
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+1 −1
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@@ -7,7 +7,7 @@ obj-y += clk-pll.o
obj-y					+= clk-pll-out.o
obj-y					+= clk-super.o
obj-y					+= clk-tegra-audio.o

obj-y					+= clk-tegra-periph.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
+596 −0

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+17 −574

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@@ -973,7 +973,7 @@ static void __init tegra20_periph_clk_init(void)

	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
		data = &tegra_periph_clk_list[i];
		clk = tegra_clk_register_periph(data->name, data->parent_names,
		clk = tegra_clk_register_periph(data->name, data->p.parent_names,
				data->num_parents, &data->periph,
				clk_base, data->offset, data->flags);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
@@ -983,7 +983,7 @@ static void __init tegra20_periph_clk_init(void)
	for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
		data = &tegra_periph_nodiv_clk_list[i];
		clk = tegra_clk_register_periph_nodiv(data->name,
					data->parent_names,
					data->p.parent_names,
					data->num_parents, &data->periph,
					clk_base, data->offset);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
+2 −2
Original line number Diff line number Diff line
@@ -1616,7 +1616,7 @@ static void __init tegra30_periph_clk_init(void)

	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
		data = &tegra_periph_clk_list[i];
		clk = tegra_clk_register_periph(data->name, data->parent_names,
		clk = tegra_clk_register_periph(data->name, data->p.parent_names,
				data->num_parents, &data->periph,
				clk_base, data->offset, data->flags);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
@@ -1626,7 +1626,7 @@ static void __init tegra30_periph_clk_init(void)
	for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
		data = &tegra_periph_nodiv_clk_list[i];
		clk = tegra_clk_register_periph_nodiv(data->name,
					data->parent_names,
					data->p.parent_names,
					data->num_parents, &data->periph,
					clk_base, data->offset);
		clk_register_clkdev(clk, data->con_id, data->dev_id);
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