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Commit 75d28b83 authored by Peter Griffin's avatar Peter Griffin Committed by Maxime Coquelin
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ARM: STi: DT: Add STiH407 family tsout0 pinctrl configuration 



tsout0 channel can be configured for either serial or parallel
data transfer. Both pin configurations are provided.

Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
parent dd72896f

arch/arm/boot/dts/stih407-pinctrl.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -568,6 +568,34 @@ 
					};

				};

			};



			tsout0 {

				pinctrl_tsout0_parallel: tsout0_parallel {

					st,pins {

						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;

						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsout0_serial: tsout0_serial {

					st,pins {

						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;

						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

					};

				};

			};

		};



		pin-controller-front1 {