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Commit 75542253 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-fixes-v4.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU fixes from Joerg Roedel:
 "A few fixes piled up:

   - Fix for a suspend/resume issue where PCI probing code overwrote
     dev->irq for the MSI irq of the AMD IOMMU.

   - Fix for a kernel crash when a 32 bit PCI device was assigned to a
     KVM guest.

   - Fix for a possible memory leak in the VT-d driver

   - A couple of fixes for the ARM-SMMU driver"

* tag 'iommu-fixes-v4.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu/amd: Fix NULL pointer deref on device detach
  iommu/amd: Prevent binding other PCI drivers to IOMMU PCI devices
  iommu/vt-d: Fix memory leak in dmar_insert_one_dev_info()
  iommu/arm-smmu: Use correct address mask for CMD_TLBI_S2_IPA
  iommu/arm-smmu: Ensure IAS is set correctly for AArch32-capable SMMUs
  iommu/io-pgtable-arm: Don't use dma_to_phys()
parents 06d1ee32 5adad991

drivers/iommu/Kconfig

+1 −2
Original line number Diff line number Diff line
@@ -23,8 +23,7 @@ config IOMMU_IO_PGTABLE 
config IOMMU_IO_PGTABLE_LPAE

	bool "ARMv7/v8 Long Descriptor Format"

	select IOMMU_IO_PGTABLE

	# SWIOTLB guarantees a dma_to_phys() implementation

	depends on ARM || ARM64 || (COMPILE_TEST && SWIOTLB)

	depends on HAS_DMA && (ARM || ARM64 || COMPILE_TEST)

	help

	  Enable support for the ARM long descriptor pagetable format.

	  This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page

drivers/iommu/amd_iommu.c

+9 −0
Original line number Diff line number Diff line
@@ -2006,6 +2006,15 @@ static void do_detach(struct iommu_dev_data *dev_data) 
{

	struct amd_iommu *iommu;



	/*

	 * First check if the device is still attached. It might already

	 * be detached from its domain because the generic

	 * iommu_detach_group code detached it and we try again here in

	 * our alias handling.

	 */

	if (!dev_data->domain)

		return;



	iommu = amd_iommu_rlookup_table[dev_data->devid];



	/* decrease reference counters */

drivers/iommu/amd_iommu_init.c

+3 −0
Original line number Diff line number Diff line
@@ -1256,6 +1256,9 @@ static int iommu_init_pci(struct amd_iommu *iommu) 
	if (!iommu->dev)

		return -ENODEV;



	/* Prevent binding other PCI device drivers to IOMMU devices */

	iommu->dev->match_driver = false;



	pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,

			      &iommu->cap);

	pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,

drivers/iommu/arm-smmu-v3.c

+15 −6
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ 
#define IDR0_TTF_SHIFT			2

#define IDR0_TTF_MASK			0x3

#define IDR0_TTF_AARCH64		(2 << IDR0_TTF_SHIFT)

#define IDR0_TTF_AARCH32_64		(3 << IDR0_TTF_SHIFT)

#define IDR0_S1P			(1 << 1)

#define IDR0_S2P			(1 << 0)
@@ -342,7 +343,8 @@ 
#define CMDQ_TLBI_0_VMID_SHIFT		32

#define CMDQ_TLBI_0_ASID_SHIFT		48

#define CMDQ_TLBI_1_LEAF		(1UL << 0)

#define CMDQ_TLBI_1_ADDR_MASK		~0xfffUL

#define CMDQ_TLBI_1_VA_MASK		~0xfffUL

#define CMDQ_TLBI_1_IPA_MASK		0xfffffffff000UL



#define CMDQ_PRI_0_SSID_SHIFT		12

#define CMDQ_PRI_0_SSID_MASK		0xfffffUL
@@ -770,11 +772,13 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) 
		break;

	case CMDQ_OP_TLBI_NH_VA:

		cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;

		/* Fallthrough */

		cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;

		break;

	case CMDQ_OP_TLBI_S2_IPA:

		cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;

		cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_ADDR_MASK;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;

		break;

	case CMDQ_OP_TLBI_NH_ASID:

		cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
@@ -2460,7 +2464,13 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu) 
	}



	/* We only support the AArch64 table format at present */

	if ((reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) < IDR0_TTF_AARCH64) {

	switch (reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) {

	case IDR0_TTF_AARCH32_64:

		smmu->ias = 40;

		/* Fallthrough */

	case IDR0_TTF_AARCH64:

		break;

	default:

		dev_err(smmu->dev, "AArch64 table format not supported!\n");

		return -ENXIO;

	}
@@ -2541,8 +2551,7 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu) 
		dev_warn(smmu->dev,

			 "failed to set DMA mask for table walker\n");



	if (!smmu->ias)

		smmu->ias = smmu->oas;

	smmu->ias = max(smmu->ias, smmu->oas);



	dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",

		 smmu->ias, smmu->oas, smmu->features);

drivers/iommu/intel-iommu.c

+1 −0
Original line number Diff line number Diff line
@@ -2301,6 +2301,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, 


	if (ret) {

		spin_unlock_irqrestore(&device_domain_lock, flags);

		free_devinfo_mem(info);

		return NULL;

	}