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Commit 7251a24e authored by Scott Wood's avatar Scott Wood
Browse files

powerpc/booke: Define MSR bits the same way as reg.h 



This ensures that all MSR definitions are consistently unsigned long,
and that MSR_CM does not become 0xffffffff80000000 (this is usually
harmless because MSR is 32-bit on booke and is mainly noticeable when
debugging, but still I'd rather avoid it).

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent cd115477

arch/powerpc/include/asm/reg_booke.h

+19 −9
Original line number Diff line number Diff line
@@ -16,15 +16,25 @@ 
#define __ASM_POWERPC_REG_BOOKE_H__



/* Machine State Register (MSR) Fields */

#define MSR_GS		(1<<28) /* Guest state */

#define MSR_UCLE	(1<<26)	/* User-mode cache lock enable */

#define MSR_SPE		(1<<25)	/* Enable SPE */

#define MSR_DWE		(1<<10)	/* Debug Wait Enable */

#define MSR_UBLE	(1<<10)	/* BTB lock enable (e500) */

#define MSR_IS		MSR_IR	/* Instruction Space */

#define MSR_DS		MSR_DR	/* Data Space */

#define MSR_PMM		(1<<2)	/* Performance monitor mark bit */

#define MSR_CM		(1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */

#define MSR_GS_LG	28	/* Guest state */

#define MSR_UCLE_LG	26	/* User-mode cache lock enable */

#define MSR_SPE_LG	25	/* Enable SPE */

#define MSR_DWE_LG	10	/* Debug Wait Enable */

#define MSR_UBLE_LG	10	/* BTB lock enable (e500) */

#define MSR_IS_LG	MSR_IR_LG /* Instruction Space */

#define MSR_DS_LG	MSR_DR_LG /* Data Space */

#define MSR_PMM_LG	2	/* Performance monitor mark bit */

#define MSR_CM_LG	31	/* Computation Mode (0=32-bit, 1=64-bit) */



#define MSR_GS		__MASK(MSR_GS_LG)

#define MSR_UCLE	__MASK(MSR_UCLE_LG)

#define MSR_SPE		__MASK(MSR_SPE_LG)

#define MSR_DWE		__MASK(MSR_DWE_LG)

#define MSR_UBLE	__MASK(MSR_UBLE_LG)

#define MSR_IS		__MASK(MSR_IS_LG)

#define MSR_DS		__MASK(MSR_DS_LG)

#define MSR_PMM		__MASK(MSR_PMM_LG)

#define MSR_CM		__MASK(MSR_CM_LG)



#if defined(CONFIG_PPC_BOOK3E_64)

#define MSR_64BIT	MSR_CM