Commit 71bbf038 authored Mar 06, 2015 by Will Deacon

dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity



The current ARM PMU binding relies on the PMU interrupts being listed in
CPU logical order, which the device-tree author simply cannot know
anything about.

This patch introduces a new "interrupt-affinity" property, which makes
the relationship between the PMU interrupts and their corresponding
CPU explicit.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent 91d57155

Documentation/devicetree/bindings/arm/pmu.txt

+7 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,13 @@ Required properties:

		Optional properties:

		- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
		to CPU nodes corresponding directly to the affinity of
		the SPIs listed in the interrupts property.

		This property should be present when there is more than
		a single SPI.

		- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
		events.