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Commit 70adc3f3 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ks8695: merge the timer header into the timer driver 



This <mach/regs-timer.h> is broadcasted in the entire kernel for
no good reason, since it's only used by the timer driver. Merge
it into the driver.

Tested-by: default avatarGreg Ungerer <gerg@snapgear.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent fea7a08a

arch/arm/mach-ks8695/include/mach/regs-timer.h

deleted100644 → 0
+0 −40
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-ks8695/include/mach/regs-timer.h

 *

 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>

 * Copyright (C) 2006 Simtec Electronics

 *

 * KS8695 - Timer registers and bit definitions.

 *

 * This file is licensed under  the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#ifndef KS8695_TIMER_H

#define KS8695_TIMER_H



#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)

#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)

#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)





/*

 * Timer registers

 */

#define KS8695_TMCON		(0x00)		/* Timer Control Register */

#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */

#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */

#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */

#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */





/* Timer Control Register */

#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */

#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */



/* Timer0 Timeout Counter Register */

#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */





#endif

arch/arm/mach-ks8695/time.c

+20 −1
Original line number Diff line number Diff line
@@ -29,11 +29,30 @@ 
#include <asm/mach/time.h>

#include <asm/system_misc.h>



#include <mach/regs-timer.h>

#include <mach/regs-irq.h>



#include "generic.h"



#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)

#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)

#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)



/*

 * Timer registers

 */

#define KS8695_TMCON		(0x00)		/* Timer Control Register */

#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */

#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */

#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */

#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */



/* Timer Control Register */

#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */

#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */



/* Timer0 Timeout Counter Register */

#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */



/*

 * Returns number of ms since last clock interrupt.  Note that interrupts

 * will have been disabled by do_gettimeoffset()