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Commit 6fa52ed3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC driver changes from Olof Johansson:
 "This is a rather large set of patches for device drivers that for one
  reason or another the subsystem maintainer preferred to get merged
  through the arm-soc tree.  There are both new drivers as well as
  existing drivers that are getting converted from platform-specific
  code into standalone drivers using the appropriate subsystem specific
  interfaces.

  In particular, we can now have pinctrl, clk, clksource and irqchip
  drivers in one file per driver, without the need to call into platform
  specific interface, or to get called from platform specific code, as
  long as all information about the hardware is provided through a
  device tree.

  Most of the drivers we touch this time are for clocksource.  Since now
  most of them are part of drivers/clocksource, I expect that we won't
  have to touch these again from arm-soc and can let the clocksource
  maintainers take care of these in the future.

  Another larger part of this series is specific to the exynos platform,
  which is seeing some significant effort in upstreaming and
  modernization of its device drivers this time around, which
  unfortunately is also the cause for the churn and a lot of the merge
  conflicts.

  There is one new subsystem that gets merged as part of this series:
  the reset controller interface, which is a very simple interface for
  taking devices on the SoC out of reset or back into reset.  Patches to
  use this interface on i.MX follow later in this merge window, and we
  are going to have other platforms (at least tegra and sirf) get
  converted in 3.11.  This will let us get rid of platform specific
  callbacks in a number of platform independent device drivers."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
  irqchip: s3c24xx: add missing __init annotations
  ARM: dts: Disable the RTC by default on exynos5
  clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
  ARM: exynos: restore mach/regs-clock.h for exynos5
  clocksource: exynos_mct: fix build error on non-DT
  pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
  irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
  reset: NULL deref on allocation failure
  reset: Add reset controller API
  dt: describe base reset signal binding
  ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
  ARM: EXYNOS: Enable PMUs for exynos4
  irqchip: exynos-combiner: Correct combined IRQs for exynos4
  irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: tegra: fix enum tegra114_clk to match binding
  ...
parents 1db77221 bc8fd900
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@@ -35,36 +35,83 @@ Required properties:

Timing properties for child nodes. All are optional and default to 0.

 - gpmc,sync-clk:	Minimum clock period for synchronous mode, in picoseconds

 Chip-select signal timings corresponding to GPMC_CONFIG2:
 - gpmc,cs-on:		Assertion time
 - gpmc,cs-rd-off:	Read deassertion time
 - gpmc,cs-wr-off:	Write deassertion time

 ADV signal timings corresponding to GPMC_CONFIG3:
 - gpmc,adv-on:		Assertion time
 - gpmc,adv-rd-off:	Read deassertion time
 - gpmc,adv-wr-off:	Write deassertion time

 WE signals timings corresponding to GPMC_CONFIG4:
 - gpmc,we-on:		Assertion time
 - gpmc,we-off:		Deassertion time

 OE signals timings corresponding to GPMC_CONFIG4:
 - gpmc,oe-on:		Assertion time
 - gpmc,oe-off:		Deassertion time

 Access time and cycle time timings corresponding to GPMC_CONFIG5:
 - gpmc,page-burst-access: Multiple access word delay
 - gpmc,access:		Start-cycle to first data valid delay
 - gpmc,rd-cycle:	Total read cycle time
 - gpmc,wr-cycle:	Total write cycle time
 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds

 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
 - gpmc,cs-on-ns:	Assertion time
 - gpmc,cs-rd-off-ns:	Read deassertion time
 - gpmc,cs-wr-off-ns:	Write deassertion time

 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
 - gpmc,adv-on-ns:	Assertion time
 - gpmc,adv-rd-off-ns:	Read deassertion time
 - gpmc,adv-wr-off-ns:	Write deassertion time

 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
 - gpmc,we-on-ns	Assertion time
 - gpmc,we-off-ns:	Deassertion time

 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
 - gpmc,oe-on-ns:	Assertion time
 - gpmc,oe-off-ns:	Deassertion time

 Access time and cycle time timings (in nanoseconds) corresponding to
 GPMC_CONFIG5:
 - gpmc,page-burst-access-ns: 	Multiple access word delay
 - gpmc,access-ns:		Start-cycle to first data valid delay
 - gpmc,rd-cycle-ns:		Total read cycle time
 - gpmc,wr-cycle-ns:		Total write cycle time
 - gpmc,bus-turnaround-ns:	Turn-around time between successive accesses
 - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses
 - gpmc,clk-activation-ns: 	GPMC clock activation time
 - gpmc,wait-monitoring-ns:	Start of wait monitoring with regard to valid
				data

Boolean timing parameters. If property is present parameter enabled and
disabled if omitted:
 - gpmc,adv-extra-delay:	ADV signal is delayed by half GPMC clock
 - gpmc,cs-extra-delay:		CS signal is delayed by half GPMC clock
 - gpmc,cycle2cycle-diffcsen:	Add "cycle2cycle-delay" between successive
				accesses to a different CS
 - gpmc,cycle2cycle-samecsen:	Add "cycle2cycle-delay" between successive
				accesses to the same CS
 - gpmc,oe-extra-delay:		OE signal is delayed by half GPMC clock
 - gpmc,we-extra-delay:		WE signal is delayed by half GPMC clock
 - gpmc,time-para-granularity:	Multiply all access times by 2

The following are only applicable to OMAP3+ and AM335x:
 - gpmc,wr-access
 - gpmc,wr-data-mux-bus

 - gpmc,wr-access-ns:		In synchronous write mode, for single or
				burst accesses, defines the number of
				GPMC_FCLK cycles from start access time
				to the GPMC_CLK rising edge used by the
				memory device for the first data capture.
 - gpmc,wr-data-mux-bus-ns:	In address-data multiplex mode, specifies
				the time when the first data is driven on
				the address-data bus.

GPMC chip-select settings properties for child nodes. All are optional.

- gpmc,burst-length	Page/burst length. Must be 4, 8 or 16.
- gpmc,burst-wrap	Enables wrap bursting
- gpmc,burst-read	Enables read page/burst mode
- gpmc,burst-write	Enables write page/burst mode
- gpmc,device-nand	Device is NAND
- gpmc,device-width	Total width of device(s) connected to a GPMC
			chip-select in bytes. The GPMC supports 8-bit
			and 16-bit devices and so this property must be
			1 or 2.
- gpmc,mux-add-data	Address and data multiplexing configuration.
			Valid values are 1 for address-address-data
			multiplexing mode and 2 for address-data
			multiplexing mode.
- gpmc,sync-read	Enables synchronous read. Defaults to asynchronous
			is this is not set.
- gpmc,sync-write	Enables synchronous writes. Defaults to asynchronous
			is this is not set.
- gpmc,wait-pin		Wait-pin used by client. Must be less than
			"gpmc,num-waitpins".
- gpmc,wait-on-read	Enables wait monitoring on reads.
- gpmc,wait-on-write	Enables wait monitoring on writes.

Example for an AM33xx board:

+288 −0
Original line number Diff line number Diff line
* Samsung Exynos4 Clock Controller

The Exynos4 clock controller generates and supplies clock to various controllers
within the Exynos4 SoC. The clock binding described here is applicable to all
SoC's in the Exynos4 family.

Required Properties:

- comptible: should be one of the following.
  - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
  - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.


		 [Core Clocks]

  Clock               ID      SoC (if specific)
  -----------------------------------------------

  xxti                1
  xusbxti             2
  fin_pll             3
  fout_apll           4
  fout_mpll           5
  fout_epll           6
  fout_vpll           7
  sclk_apll           8
  sclk_mpll           9
  sclk_epll           10
  sclk_vpll           11
  arm_clk             12
  aclk200             13
  aclk100             14
  aclk160             15
  aclk133             16
  mout_mpll_user_t    17      Exynos4x12
  mout_mpll_user_c    18      Exynos4x12
  mout_core           19
  mout_apll           20


            [Clock Gate for Special Clocks]

  Clock               ID      SoC (if specific)
  -----------------------------------------------

  sclk_fimc0          128
  sclk_fimc1          129
  sclk_fimc2          130
  sclk_fimc3          131
  sclk_cam0           132
  sclk_cam1           133
  sclk_csis0          134
  sclk_csis1          135
  sclk_hdmi           136
  sclk_mixer          137
  sclk_dac            138
  sclk_pixel          139
  sclk_fimd0          140
  sclk_mdnie0         141     Exynos4412
  sclk_mdnie_pwm0 12  142     Exynos4412
  sclk_mipi0          143
  sclk_audio0         144
  sclk_mmc0           145
  sclk_mmc1           146
  sclk_mmc2           147
  sclk_mmc3           148
  sclk_mmc4           149
  sclk_sata           150     Exynos4210
  sclk_uart0          151
  sclk_uart1          152
  sclk_uart2          153
  sclk_uart3          154
  sclk_uart4          155
  sclk_audio1         156
  sclk_audio2         157
  sclk_spdif          158
  sclk_spi0           159
  sclk_spi1           160
  sclk_spi2           161
  sclk_slimbus        162
  sclk_fimd1          163     Exynos4210
  sclk_mipi1          164     Exynos4210
  sclk_pcm1           165
  sclk_pcm2           166
  sclk_i2s1           167
  sclk_i2s2           168
  sclk_mipihsi        169     Exynos4412
  sclk_mfc            170
  sclk_pcm0           171
  sclk_g3d            172
  sclk_pwm_isp        173     Exynos4x12
  sclk_spi0_isp       174     Exynos4x12
  sclk_spi1_isp       175     Exynos4x12
  sclk_uart_isp       176     Exynos4x12

	      [Peripheral Clock Gates]

  Clock               ID      SoC (if specific)
  -----------------------------------------------

  fimc0               256
  fimc1               257
  fimc2               258
  fimc3               259
  csis0               260
  csis1               261
  jpeg                262
  smmu_fimc0          263
  smmu_fimc1          264
  smmu_fimc2          265
  smmu_fimc3          266
  smmu_jpeg           267
  vp                  268
  mixer               269
  tvenc               270     Exynos4210
  hdmi                271
  smmu_tv             272
  mfc                 273
  smmu_mfcl           274
  smmu_mfcr           275
  g3d                 276
  g2d                 277     Exynos4210
  rotator             278     Exynos4210
  mdma                279     Exynos4210
  smmu_g2d            280     Exynos4210
  smmu_rotator        281     Exynos4210
  smmu_mdma           282     Exynos4210
  fimd0               283
  mie0                284
  mdnie0              285     Exynos4412
  dsim0               286
  smmu_fimd0          287
  fimd1               288     Exynos4210
  mie1                289     Exynos4210
  dsim1               290     Exynos4210
  smmu_fimd1          291     Exynos4210
  pdma0               292
  pdma1               293
  pcie_phy            294
  sata_phy            295     Exynos4210
  tsi                 296
  sdmmc0              297
  sdmmc1              298
  sdmmc2              299
  sdmmc3              300
  sdmmc4              301
  sata                302     Exynos4210
  sromc               303
  usb_host            304
  usb_device          305
  pcie                306
  onenand             307
  nfcon               308
  smmu_pcie           309
  gps                 310
  smmu_gps            311
  uart0               312
  uart1               313
  uart2               314
  uart3               315
  uart4               316
  i2c0                317
  i2c1                318
  i2c2                319
  i2c3                320
  i2c4                321
  i2c5                322
  i2c6                323
  i2c7                324
  i2c_hdmi            325
  tsadc               326
  spi0                327
  spi1                328
  spi2                329
  i2s1                330
  i2s2                331
  pcm0                332
  i2s0                333
  pcm1                334
  pcm2                335
  pwm                 336
  slimbus             337
  spdif               338
  ac97                339
  modemif             340
  chipid              341
  sysreg              342
  hdmi_cec            343
  mct                 344
  wdt                 345
  rtc                 346
  keyif               347
  audss               348
  mipi_hsi            349     Exynos4210
  mdma2               350     Exynos4210
  pixelasyncm0        351
  pixelasyncm1        352
  fimc_lite0          353     Exynos4x12
  fimc_lite1          354     Exynos4x12
  ppmuispx            355     Exynos4x12
  ppmuispmx           356     Exynos4x12
  fimc_isp            357     Exynos4x12
  fimc_drc            358     Exynos4x12
  fimc_fd             359     Exynos4x12
  mcuisp              360     Exynos4x12
  gicisp              361     Exynos4x12
  smmu_isp            362     Exynos4x12
  smmu_drc            363     Exynos4x12
  smmu_fd             364     Exynos4x12
  smmu_lite0          365     Exynos4x12
  smmu_lite1          366     Exynos4x12
  mcuctl_isp          367     Exynos4x12
  mpwm_isp            368     Exynos4x12
  i2c0_isp            369     Exynos4x12
  i2c1_isp            370     Exynos4x12
  mtcadc_isp          371     Exynos4x12
  pwm_isp             372     Exynos4x12
  wdt_isp             373     Exynos4x12
  uart_isp            374     Exynos4x12
  asyncaxim           375     Exynos4x12
  smmu_ispcx          376     Exynos4x12
  spi0_isp            377     Exynos4x12
  spi1_isp            378     Exynos4x12
  pwm_isp_sclk        379     Exynos4x12
  spi0_isp_sclk       380     Exynos4x12
  spi1_isp_sclk       381     Exynos4x12
  uart_isp_sclk       382     Exynos4x12

		[Mux Clocks]

  Clock			ID	SoC (if specific)
  -----------------------------------------------

  mout_fimc0		384
  mout_fimc1		385
  mout_fimc2		386
  mout_fimc3		387
  mout_cam0		388
  mout_cam1		389
  mout_csis0		390
  mout_csis1		391
  mout_g3d0		392
  mout_g3d1		393
  mout_g3d		394
  aclk400_mcuisp	395	Exynos4x12

		[Div Clocks]

  Clock			ID	SoC (if specific)
  -----------------------------------------------

  div_isp0		450	Exynos4x12
  div_isp1		451	Exynos4x12
  div_mcuisp0		452	Exynos4x12
  div_mcuisp1		453	Exynos4x12
  div_aclk200		454	Exynos4x12
  div_aclk400_mcuisp	455	Exynos4x12


Example 1: An example of a clock controller node is listed below.

	clock: clock-controller@0x10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

Example 2: UART controller node that consumes the clock generated by the clock
	   controller. Refer to the standard clock bindings for information
	   about 'clocks' and 'clock-names' property.

	serial@13820000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 314>, <&clock 153>;
		clock-names = "uart", "clk_uart_baud0";
	};
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* Samsung Exynos5250 Clock Controller

The Exynos5250 clock controller generates and supplies clock to various
controllers within the Exynos5250 SoC.

Required Properties:

- comptible: should be one of the following.
  - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.


       [Core Clocks]

  Clock			ID
  ----------------------------

  fin_pll		1

  [Clock Gate for Special Clocks]

  Clock			ID
  ----------------------------

  sclk_cam_bayer	128
  sclk_cam0		129
  sclk_cam1		130
  sclk_gscl_wa		131
  sclk_gscl_wb		132
  sclk_fimd1		133
  sclk_mipi1		134
  sclk_dp		135
  sclk_hdmi		136
  sclk_pixel		137
  sclk_audio0		138
  sclk_mmc0		139
  sclk_mmc1		140
  sclk_mmc2		141
  sclk_mmc3		142
  sclk_sata		143
  sclk_usb3		144
  sclk_jpeg		145
  sclk_uart0		146
  sclk_uart1		147
  sclk_uart2		148
  sclk_uart3		149
  sclk_pwm		150
  sclk_audio1		151
  sclk_audio2		152
  sclk_spdif		153
  sclk_spi0		154
  sclk_spi1		155
  sclk_spi2		156


   [Peripheral Clock Gates]

  Clock			ID
  ----------------------------

  gscl0			256
  gscl1			257
  gscl2			258
  gscl3			259
  gscl_wa		260
  gscl_wb		261
  smmu_gscl0		262
  smmu_gscl1		263
  smmu_gscl2		264
  smmu_gscl3		265
  mfc			266
  smmu_mfcl		267
  smmu_mfcr		268
  rotator		269
  jpeg			270
  mdma1			271
  smmu_rotator		272
  smmu_jpeg		273
  smmu_mdma1		274
  pdma0			275
  pdma1			276
  sata			277
  usbotg		278
  mipi_hsi		279
  sdmmc0		280
  sdmmc1		281
  sdmmc2		282
  sdmmc3		283
  sromc			284
  usb2			285
  usb3			286
  sata_phyctrl		287
  sata_phyi2c		288
  uart0			289
  uart1			290
  uart2			291
  uart3			292
  uart4			293
  i2c0			294
  i2c1			295
  i2c2			296
  i2c3			297
  i2c4			298
  i2c5			299
  i2c6			300
  i2c7			301
  i2c_hdmi		302
  adc			303
  spi0			304
  spi1			305
  spi2			306
  i2s1			307
  i2s2			308
  pcm1			309
  pcm2			310
  pwm			311
  spdif			312
  ac97			313
  hsi2c0		314
  hsi2c1		315
  hs12c2		316
  hs12c3		317
  chipid		318
  sysreg		319
  pmu			320
  cmu_top		321
  cmu_core		322
  cmu_mem		323
  tzpc0			324
  tzpc1			325
  tzpc2			326
  tzpc3			327
  tzpc4			328
  tzpc5			329
  tzpc6			330
  tzpc7			331
  tzpc8			332
  tzpc9			333
  hdmi_cec		334
  mct			335
  wdt			336
  rtc			337
  tmu			338
  fimd1			339
  mie1			340
  dsim0			341
  dp			342
  mixer			343
  hdmi			345

Example 1: An example of a clock controller node is listed below.

	clock: clock-controller@0x10010000 {
		compatible = "samsung,exynos5250-clock";
		reg = <0x10010000 0x30000>;
		#clock-cells = <1>;
	};

Example 2: UART controller node that consumes the clock generated by the clock
	   controller. Refer to the standard clock bindings for information
	   about 'clocks' and 'clock-names' property.

	serial@13820000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 314>, <&clock 153>;
		clock-names = "uart", "clk_uart_baud0";
	};
+61 −0
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* Samsung Exynos5440 Clock Controller

The Exynos5440 clock controller generates and supplies clock to various
controllers within the Exynos5440 SoC.

Required Properties:

- comptible: should be "samsung,exynos5440-clock".

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.


       [Core Clocks]

  Clock			ID
  ----------------------------

  xtal			1
  arm_clk		2

   [Peripheral Clock Gates]

  Clock			ID
  ----------------------------

  spi_baud		16
  pb0_250		17
  pr0_250		18
  pr1_250		19
  b_250			20
  b_125			21
  b_200			22
  sata			23
  usb			24
  gmac0			25
  cs250			26
  pb0_250_o		27
  pr0_250_o		28
  pr1_250_o		29
  b_250_o		30
  b_125_o		31
  b_200_o		32
  sata_o		33
  usb_o			34
  gmac0_o		35
  cs250_o		36

Example: An example of a clock controller node is listed below.

	clock: clock-controller@0x10010000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x10000>;
		#clock-cells = <1>;
	};
+303 −0
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NVIDIA Tegra114 Clock And Reset Controller

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt

The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.

Required properties :
- compatible : Should be "nvidia,tegra114-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
  In clock consumers, this cell represents the clock ID exposed by the CAR.

  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  registers. These IDs often match those in the CAR's RST_DEVICES registers,
  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  this case, those clocks are assigned IDs above 160 in order to highlight
  this issue. Implementations that interpret these clock IDs as bit values
  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  explicitly handle these special cases.

  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  above.

  0	unassigned
  1	unassigned
  2	unassigned
  3	unassigned
  4	rtc
  5	timer
  6	uarta
  7	unassigned	(register bit affects uartb and vfir)
  8	unassigned
  9	sdmmc2
  10	unassigned	(register bit affects spdif_in and spdif_out)
  11	i2s1
  12	i2c1
  13	ndflash
  14	sdmmc1
  15	sdmmc4
  16	unassigned
  17	pwm
  18	i2s2
  19	epp
  20	unassigned	(register bit affects vi and vi_sensor)
  21	2d
  22	usbd
  23	isp
  24	3d
  25	unassigned
  26	disp2
  27	disp1
  28	host1x
  29	vcp
  30	i2s0
  31	unassigned

  32	unassigned
  33	unassigned
  34	apbdma
  35	unassigned
  36	kbc
  37	unassigned
  38	unassigned
  39	unassigned	(register bit affects fuse and fuse_burn)
  40	kfuse
  41	sbc1
  42	nor
  43	unassigned
  44	sbc2
  45	unassigned
  46	sbc3
  47	i2c5
  48	dsia
  49	unassigned
  50	mipi
  51	hdmi
  52	csi
  53	unassigned
  54	i2c2
  55	uartc
  56	mipi-cal
  57	emc
  58	usb2
  59	usb3
  60	msenc
  61	vde
  62	bsea
  63	bsev

  64	unassigned
  65	uartd
  66	unassigned
  67	i2c3
  68	sbc4
  69	sdmmc3
  70	unassigned
  71	owr
  72	afi
  73	csite
  74	unassigned
  75	unassigned
  76	la
  77	trace
  78	soc_therm
  79	dtv
  80	ndspeed
  81	i2cslow
  82	dsib
  83	tsec
  84	unassigned
  85	unassigned
  86	unassigned
  87	unassigned
  88	unassigned
  89	xusb_host
  90	unassigned
  91	msenc
  92	csus
  93	unassigned
  94	unassigned
  95	unassigned	(bit affects xusb_dev and xusb_dev_src)

  96	unassigned
  97	unassigned
  98	unassigned
  99	mselect
  100	tsensor
  101	i2s3
  102	i2s4
  103	i2c4
  104	sbc5
  105	sbc6
  106	d_audio
  107	apbif
  108	dam0
  109	dam1
  110	dam2
  111	hda2codec_2x
  112	unassigned
  113	audio0_2x
  114	audio1_2x
  115	audio2_2x
  116	audio3_2x
  117	audio4_2x
  118	spdif_2x
  119	actmon
  120	extern1
  121	extern2
  122	extern3
  123	unassigned
  124	unassigned
  125	hda
  126	unassigned
  127	se

  128	hda2hdmi
  129	unassigned
  130	unassigned
  131	unassigned
  132	unassigned
  133	unassigned
  134	unassigned
  135	unassigned
  136	unassigned
  137	unassigned
  138	unassigned
  139	unassigned
  140	unassigned
  141	unassigned
  142	unassigned
  143	unassigned	(bit affects xusb_falcon_src, xusb_fs_src,
			 xusb_host_src and xusb_ss_src)
  144	cilab
  145	cilcd
  146	cile
  147	dsialp
  148	dsiblp
  149	unassigned
  150	dds
  151	unassigned
  152	dp2
  153	amx
  154	adx
  155	unassigned	(bit affects dfll_ref and dfll_soc)
  156	xusb_ss

  192	uartb
  193	vfir
  194	spdif_in
  195	spdif_out
  196	vi
  197	vi_sensor
  198	fuse
  199	fuse_burn
  200	clk_32k
  201	clk_m
  202	clk_m_div2
  203	clk_m_div4
  204	pll_ref
  205	pll_c
  206	pll_c_out1
  207	pll_c2
  208	pll_c3
  209	pll_m
  210	pll_m_out1
  211	pll_p
  212	pll_p_out1
  213	pll_p_out2
  214	pll_p_out3
  215	pll_p_out4
  216	pll_a
  217	pll_a_out0
  218	pll_d
  219	pll_d_out0
  220	pll_d2
  221	pll_d2_out0
  222	pll_u
  223	pll_u_480M
  224	pll_u_60M
  225	pll_u_48M
  226	pll_u_12M
  227	pll_x
  228	pll_x_out0
  229	pll_re_vco
  230	pll_re_out
  231	pll_e_out0
  232	spdif_in_sync
  233	i2s0_sync
  234	i2s1_sync
  235	i2s2_sync
  236	i2s3_sync
  237	i2s4_sync
  238	vimclk_sync
  239	audio0
  240	audio1
  241	audio2
  242	audio3
  243	audio4
  244	spdif
  245	clk_out_1
  246	clk_out_2
  247	clk_out_3
  248	blink
  252	xusb_host_src
  253	xusb_falcon_src
  254	xusb_fs_src
  255	xusb_ss_src
  256	xusb_dev_src
  257	xusb_dev
  258	xusb_hs_src
  259	sclk
  260	hclk
  261	pclk
  262	cclk_g
  263	cclk_lp
  264	dfll_ref
  265	dfll_soc

Example SoC include file:

/ {
	tegra_car: clock {
		compatible = "nvidia,tegra114-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	usb@c5004000 {
		clocks = <&tegra_car 58>; /* usb2 */
	};
};

Example board file:

/ {
	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		osc: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		clk_32k: clock@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	&tegra_car {
		clocks = <&clk_32k> <&osc>;
	};
};
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