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Commit 6f72a631 authored by Christian König's avatar Christian König
Browse files

drm/radeon: remove r600_blit_suspend



Just reinitialize the shader content on resume instead.

Signed-off-by: default avatarChristian König <deathsimple@vodafone.de>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2898c348
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+0 −1
Original line number Diff line number Diff line
@@ -3139,7 +3139,6 @@ int evergreen_suspend(struct radeon_device *rdev)
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r600_audio_fini(rdev);
	r600_blit_suspend(rdev);
	r700_cp_stop(rdev);
	ring->ready = false;
	evergreen_irq_suspend(rdev);
+20 −20
Original line number Diff line number Diff line
@@ -634,10 +634,6 @@ int evergreen_blit_init(struct radeon_device *rdev)

	rdev->r600_blit.max_dim = 16384;

	/* pin copy shader into vram if already initialized */
	if (rdev->r600_blit.shader_obj)
		goto done;

	rdev->r600_blit.state_offset = 0;

	if (rdev->family < CHIP_CAYMAN)
@@ -668,13 +664,28 @@ int evergreen_blit_init(struct radeon_device *rdev)
		obj_size += cayman_ps_size * 4;
	obj_size = ALIGN(obj_size, 256);

	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
	/* pin copy shader into vram if not already initialized */
	if (!rdev->r600_blit.shader_obj) {
		r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_VRAM,
				     NULL, &rdev->r600_blit.shader_obj);
		if (r) {
			DRM_ERROR("evergreen failed to allocate shader\n");
			return r;
		}

		r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
				  &rdev->r600_blit.shader_gpu_addr);
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
			return r;
		}
	}

	DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
		  obj_size,
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
@@ -714,17 +725,6 @@ int evergreen_blit_init(struct radeon_device *rdev)
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);

done:
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->r600_blit.shader_gpu_addr);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
	if (r) {
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
		return r;
	}
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
	return 0;
}
+0 −1
Original line number Diff line number Diff line
@@ -1316,7 +1316,6 @@ int cayman_suspend(struct radeon_device *rdev)
{
	r600_audio_fini(rdev);
	radeon_vm_manager_suspend(rdev);
	r600_blit_suspend(rdev);
	cayman_cp_enable(rdev, false);
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
	evergreen_irq_suspend(rdev);
+0 −15
Original line number Diff line number Diff line
@@ -2307,20 +2307,6 @@ int r600_copy_blit(struct radeon_device *rdev,
	return 0;
}

void r600_blit_suspend(struct radeon_device *rdev)
{
	int r;

	/* unpin shaders bo */
	if (rdev->r600_blit.shader_obj) {
		r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
		if (!r) {
			radeon_bo_unpin(rdev->r600_blit.shader_obj);
			radeon_bo_unreserve(rdev->r600_blit.shader_obj);
		}
	}
}

int r600_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size)
@@ -2461,7 +2447,6 @@ int r600_resume(struct radeon_device *rdev)
int r600_suspend(struct radeon_device *rdev)
{
	r600_audio_fini(rdev);
	r600_blit_suspend(rdev);
	r600_cp_stop(rdev);
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
	r600_irq_suspend(rdev);
+20 −20
Original line number Diff line number Diff line
@@ -524,10 +524,6 @@ int r600_blit_init(struct radeon_device *rdev)

	rdev->r600_blit.max_dim = 8192;

	/* pin copy shader into vram if already initialized */
	if (rdev->r600_blit.shader_obj)
		goto done;

	rdev->r600_blit.state_offset = 0;

	if (rdev->family >= CHIP_RV770)
@@ -552,13 +548,28 @@ int r600_blit_init(struct radeon_device *rdev)
	obj_size += r6xx_ps_size * 4;
	obj_size = ALIGN(obj_size, 256);

	r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
	/* pin copy shader into vram if not already initialized */
	if (rdev->r600_blit.shader_obj == NULL) {
		r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_VRAM,
				     NULL, &rdev->r600_blit.shader_obj);
		if (r) {
			DRM_ERROR("r600 failed to allocate shader\n");
			return r;
		}

		r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
		if (unlikely(r != 0))
			return r;
		r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
				  &rdev->r600_blit.shader_gpu_addr);
		radeon_bo_unreserve(rdev->r600_blit.shader_obj);
		if (r) {
			dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
			return r;
		}
	}

	DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
		  obj_size,
		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
@@ -587,17 +598,6 @@ int r600_blit_init(struct radeon_device *rdev)
	radeon_bo_kunmap(rdev->r600_blit.shader_obj);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);

done:
	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
			  &rdev->r600_blit.shader_gpu_addr);
	radeon_bo_unreserve(rdev->r600_blit.shader_obj);
	if (r) {
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
		return r;
	}
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
	return 0;
}
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