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Commit 6f6e68b3 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next 

This is the main 4.8 pull for radeon and amdgpu.  Sorry for the delay,
I meant to send this out last week, but I was moving house.  Lots of
changes here:
- ATPX improvements for better dGPU power control on PX systems
- New power features for CZ/BR/ST
- Pipelined BO moves and evictions in TTM
- GPU scheduler improvements
- GPU reset improvements
- Overclocking on dGPUs with amdgpu
- Lots of code cleanup
- Bug fixes

* 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (191 commits)
  drm/amd/powerplay: don't add invalid voltage.
  drm/amdgpu: add read/write function for GC CAC programming
  drm/amd/powerplay: add definitions related to di/dt feature for fiji and polaris.
  drm/amd/powerplay: add shared definitions for di/dt feature.
  drm/amdgpu: remove gfx8 registers that vary between asics
  drm/amd/powerplay: add mvdd dpm support.
  drm/amdgpu: get number of shade engine by cgs interface.
  drm/amdgpu: remove more of the ring backup code
  drm/amd/powerplay:  Unify family defines
  drm/amdgpu: clean up ring_backup code, no need more
  drm/amdgpu: ib test first after gpu reset
  drm/amdgpu: recovery hw jobs when gpu reset V3
  drm/amdgpu: abstract amdgpu_vm_is_gpu_reset
  drm/amdgpu: add a bool to specify if needing vm flush V2
  drm/amdgpu: add amd_sched_job_recovery
  drm/amdgpu: force completion for gpu reset
  drm/amdgpu: block ttm first before parking scheduler
  drm/amd: add amd_sched_hw_job_reset
  drm/amd: add parent for sched fence
  drm/amdgpu: remove evict vram
  ...
parents b33e0773 b1814a1d

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+67 −29
Original line number Diff line number Diff line
@@ -85,8 +85,12 @@ extern int amdgpu_vm_debug; 
extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_powerplay;

extern int amdgpu_powercontainment;

extern unsigned amdgpu_pcie_gen_cap;

extern unsigned amdgpu_pcie_lane_cap;

extern unsigned amdgpu_cg_mask;

extern unsigned amdgpu_pg_mask;

extern char *amdgpu_disable_cu;



#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
@@ -183,6 +187,10 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 
int amdgpu_set_powergating_state(struct amdgpu_device *adev,

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state);

int amdgpu_wait_for_idle(struct amdgpu_device *adev,

			 enum amd_ip_block_type block_type);

bool amdgpu_is_idle(struct amdgpu_device *adev,

		    enum amd_ip_block_type block_type);



struct amdgpu_ip_block_version {

	enum amd_ip_block_type type;
@@ -594,11 +602,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, 
		     struct amdgpu_sync *sync,

		     struct reservation_object *resv,

		     void *owner);

bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);

int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,

			     struct fence *fence);

struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,

				     struct amdgpu_ring *ring);

struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

int amdgpu_sync_wait(struct amdgpu_sync *sync);

void amdgpu_sync_free(struct amdgpu_sync *sync);

int amdgpu_sync_init(void);

void amdgpu_sync_fini(void);
@@ -754,12 +760,11 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 
int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

void amdgpu_job_free_func(struct kref *refcount);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct amd_sched_entity *entity, void *owner,

		      struct fence **f);

void amdgpu_job_timeout_func(struct work_struct *work);



struct amdgpu_ring {

	struct amdgpu_device		*adev;
@@ -771,8 +776,6 @@ struct amdgpu_ring { 
	struct amdgpu_bo	*ring_obj;

	volatile uint32_t	*ring;

	unsigned		rptr_offs;

	u64			next_rptr_gpu_addr;

	volatile u32		*next_rptr_cpu_addr;

	unsigned		wptr;

	unsigned		wptr_old;

	unsigned		ring_size;
@@ -791,7 +794,6 @@ struct amdgpu_ring { 
	u32			doorbell_index;

	bool			use_doorbell;

	unsigned		wptr_offs;

	unsigned		next_rptr_offs;

	unsigned		fence_offs;

	uint64_t		current_ctx;

	enum amdgpu_ring_type	type;
@@ -799,6 +801,9 @@ struct amdgpu_ring { 
	unsigned		cond_exe_offs;

	u64				cond_exe_gpu_addr;

	volatile u32	*cond_exe_cpu_addr;

#if defined(CONFIG_DEBUG_FS)

	struct dentry *ent;

#endif

};



/*
@@ -861,6 +866,7 @@ struct amdgpu_vm { 
	struct amdgpu_bo	*page_directory;

	unsigned		max_pde_used;

	struct fence		*page_directory_fence;

	uint64_t		last_eviction_counter;



	/* array of page tables, one for each page directory entry */

	struct amdgpu_vm_pt	*page_tables;
@@ -883,13 +889,14 @@ struct amdgpu_vm_id { 
	struct fence		*first;

	struct amdgpu_sync	active;

	struct fence		*last_flush;

	struct amdgpu_ring      *last_user;

	atomic64_t		owner;



	uint64_t		pd_gpu_addr;

	/* last flushed PD/PT update */

	struct fence		*flushed_updates;



	uint32_t                current_gpu_reset_count;



	uint32_t		gds_base;

	uint32_t		gds_size;

	uint32_t		gws_base;
@@ -905,6 +912,10 @@ struct amdgpu_vm_manager { 
	struct list_head			ids_lru;

	struct amdgpu_vm_id			ids[AMDGPU_NUM_VM];



	/* Handling of VM fences */

	u64					fence_context;

	unsigned				seqno[AMDGPU_MAX_RINGS];



	uint32_t				max_pfn;

	/* vram base address for page table entry  */

	u64					vram_base_offset;
@@ -926,17 +937,14 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 
void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,

			 struct list_head *validated,

			 struct amdgpu_bo_list_entry *entry);

void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);

void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,

			  struct list_head *duplicates);

void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,

				  struct amdgpu_vm *vm);

int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,

		      struct amdgpu_sync *sync, struct fence *fence,

		      unsigned *vm_id, uint64_t *vm_pd_addr);

int amdgpu_vm_flush(struct amdgpu_ring *ring,

		    unsigned vm_id, uint64_t pd_addr,

		    uint32_t gds_base, uint32_t gds_size,

		    uint32_t gws_base, uint32_t gws_size,

		    uint32_t oa_base, uint32_t oa_size);

		      struct amdgpu_job *job);

int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);

void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);

uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);

int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
@@ -1142,6 +1150,12 @@ struct amdgpu_cu_info { 
	uint32_t bitmap[4][4];

};



struct amdgpu_gfx_funcs {

	/* get the gpu clock counter */

	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);

};



struct amdgpu_gfx {

	struct mutex			gpu_clock_mutex;

	struct amdgpu_gca_config	config;
@@ -1178,6 +1192,7 @@ struct amdgpu_gfx { 
	/* ce ram size*/

	unsigned			ce_ram_size;

	struct amdgpu_cu_info		cu_info;

	const struct amdgpu_gfx_funcs	*funcs;

};



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1195,10 +1210,6 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);

void amdgpu_ring_commit(struct amdgpu_ring *ring);

void amdgpu_ring_undo(struct amdgpu_ring *ring);

unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,

			    uint32_t **data);

int amdgpu_ring_restore(struct amdgpu_ring *ring,

			unsigned size, uint32_t *data);

int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,

		     unsigned ring_size, u32 nop, u32 align_mask,

		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
@@ -1250,6 +1261,7 @@ struct amdgpu_job { 
	uint32_t		num_ibs;

	void			*owner;

	uint64_t		ctx;

	bool                    vm_needs_flush;

	unsigned		vm_id;

	uint64_t		vm_pd_addr;

	uint32_t		gds_base, gds_size;
@@ -1257,8 +1269,7 @@ struct amdgpu_job { 
	uint32_t		oa_base, oa_size;



	/* user fence handling */

	struct amdgpu_bo	*uf_bo;

	uint32_t		uf_offset;

	uint64_t		uf_addr;

	uint64_t		uf_sequence;



};
@@ -1560,6 +1571,12 @@ struct amdgpu_dpm_funcs { 
	u32 (*get_fan_control_mode)(struct amdgpu_device *adev);

	int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);

	int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);

	int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);

	int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);

	int (*get_sclk_od)(struct amdgpu_device *adev);

	int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);

	int (*get_mclk_od)(struct amdgpu_device *adev);

	int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);

};



struct amdgpu_dpm {
@@ -1767,6 +1784,8 @@ int amdgpu_debugfs_init(struct drm_minor *minor); 
void amdgpu_debugfs_cleanup(struct drm_minor *minor);

#endif



int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);



/*

 * amdgpu smumgr functions

 */
@@ -1811,12 +1830,8 @@ struct amdgpu_asic_funcs { 
			     u32 sh_num, u32 reg_offset, u32 *value);

	void (*set_vga_state)(struct amdgpu_device *adev, bool state);

	int (*reset)(struct amdgpu_device *adev);

	/* wait for mc_idle */

	int (*wait_for_mc_idle)(struct amdgpu_device *adev);

	/* get the reference clock */

	u32 (*get_xclk)(struct amdgpu_device *adev);

	/* get the gpu clock counter */

	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	/* MM block clocks */

	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
@@ -2003,6 +2018,10 @@ struct amdgpu_device { 
	spinlock_t didt_idx_lock;

	amdgpu_rreg_t			didt_rreg;

	amdgpu_wreg_t			didt_wreg;

	/* protects concurrent gc_cac register access */

	spinlock_t gc_cac_idx_lock;

	amdgpu_rreg_t			gc_cac_rreg;

	amdgpu_wreg_t			gc_cac_wreg;

	/* protects concurrent ENDPOINT (audio) register access */

	spinlock_t audio_endpt_idx_lock;

	amdgpu_block_rreg_t		audio_endpt_rreg;
@@ -2028,6 +2047,7 @@ struct amdgpu_device { 
	atomic64_t			vram_vis_usage;

	atomic64_t			gtt_usage;

	atomic64_t			num_bytes_moved;

	atomic64_t			num_evictions;

	atomic_t			gpu_reset_counter;



	/* display */
@@ -2131,6 +2151,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))

#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))

#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))

#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))

#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))

#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))

#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))

#define WREG32_P(reg, val, mask)				\
@@ -2206,12 +2228,10 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
 */

#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))

#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))

#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))

#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))

#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))

#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))

#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))

#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
@@ -2264,6 +2284,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))

#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))

#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))



#define amdgpu_dpm_get_temperature(adev) \

	((adev)->pp_enabled ?						\
@@ -2342,6 +2364,18 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_dpm_force_clock_level(adev, type, level) \

		(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)



#define amdgpu_dpm_get_sclk_od(adev) \

	(adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)



#define amdgpu_dpm_set_sclk_od(adev, value) \

	(adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)



#define amdgpu_dpm_get_mclk_od(adev) \

	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))



#define amdgpu_dpm_set_mclk_od(adev, value) \

	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))



#define amdgpu_dpm_dispatch_task(adev, event_id, input, output)		\

	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
@@ -2383,9 +2417,13 @@ bool amdgpu_device_is_px(struct drm_device *dev); 
#if defined(CONFIG_VGA_SWITCHEROO)

void amdgpu_register_atpx_handler(void);

void amdgpu_unregister_atpx_handler(void);

bool amdgpu_has_atpx_dgpu_power_cntl(void);

bool amdgpu_is_atpx_hybrid(void);

#else

static inline void amdgpu_register_atpx_handler(void) {}

static inline void amdgpu_unregister_atpx_handler(void) {}

static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }

static inline bool amdgpu_is_atpx_hybrid(void) { return false; }

#endif



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+2 −2
Original line number Diff line number Diff line
@@ -240,8 +240,8 @@ uint64_t get_gpu_clock_counter(struct kgd_dev *kgd) 
{

	struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;



	if (rdev->asic_funcs->get_gpu_clock_counter)

		return rdev->asic_funcs->get_gpu_clock_counter(rdev);

	if (rdev->gfx.funcs->get_gpu_clock_counter)

		return rdev->gfx.funcs->get_gpu_clock_counter(rdev);

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

+49 −17
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/slab.h>

#include <linux/acpi.h>

#include <linux/pci.h>

#include <linux/delay.h>



#include "amd_acpi.h"
@@ -27,6 +28,7 @@ struct amdgpu_atpx_functions { 
struct amdgpu_atpx {

	acpi_handle handle;

	struct amdgpu_atpx_functions functions;

	bool is_hybrid;

};



static struct amdgpu_atpx_priv {
@@ -63,6 +65,14 @@ bool amdgpu_has_atpx(void) { 
	return amdgpu_atpx_priv.atpx_detected;

}



bool amdgpu_has_atpx_dgpu_power_cntl(void) {

	return amdgpu_atpx_priv.atpx.functions.power_cntl;

}



bool amdgpu_is_atpx_hybrid(void) {

	return amdgpu_atpx_priv.atpx.is_hybrid;

}



/**

 * amdgpu_atpx_call - call an ATPX method

 *
@@ -142,18 +152,12 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas 
 */

static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)

{

	/* make sure required functions are enabled */

	/* dGPU power control is required */

	if (atpx->functions.power_cntl == false) {

		printk("ATPX dGPU power cntl not present, forcing\n");

		atpx->functions.power_cntl = true;

	}

	u32 valid_bits = 0;



	if (atpx->functions.px_params) {

		union acpi_object *info;

		struct atpx_px_params output;

		size_t size;

		u32 valid_bits;



		info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_GET_PX_PARAMETERS, NULL);

		if (!info)
@@ -172,6 +176,10 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) 
		memcpy(&output, info->buffer.pointer, size);



		valid_bits = output.flags & output.valid_flags;



		kfree(info);

	}



	/* if separate mux flag is set, mux controls are required */

	if (valid_bits & ATPX_SEPARATE_MUX_FOR_I2C) {

		atpx->functions.i2c_mux_cntl = true;
@@ -183,8 +191,28 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) 
			  ATPX_DFP_SIGNAL_MUXED))

		atpx->functions.disp_mux_cntl = true;



		kfree(info);



	/* some bioses set these bits rather than flagging power_cntl as supported */

	if (valid_bits & (ATPX_DYNAMIC_PX_SUPPORTED |

			  ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED))

		atpx->functions.power_cntl = true;



	atpx->is_hybrid = false;

	if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {

		printk("ATPX Hybrid Graphics\n");

#if 1

		/* This is a temporary hack until the D3 cold support

		 * makes it upstream.  The ATPX power_control method seems

		 * to still work on even if the system should be using

		 * the new standardized hybrid D3 cold ACPI interface.

		 */

		atpx->functions.power_cntl = true;

#else

		atpx->functions.power_cntl = false;

#endif

		atpx->is_hybrid = true;

	}



	return 0;

}
@@ -259,6 +287,10 @@ static int amdgpu_atpx_set_discrete_state(struct amdgpu_atpx *atpx, u8 state) 
		if (!info)

			return -EIO;

		kfree(info);



		/* 200ms delay is required after off */

		if (state == 0)

			msleep(200);

	}

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

+3 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
	unsigned last_entry = 0, first_userptr = num_entries;

	unsigned i;

	int r;

	unsigned long total_size = 0;



	array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry));

	if (!array)
@@ -140,6 +141,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
		if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_OA)

			oa_obj = entry->robj;



		total_size += amdgpu_bo_size(entry->robj);

		trace_amdgpu_bo_list_set(list, entry->robj);

	}
@@ -155,6 +157,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
	list->array = array;

	list->num_entries = num_entries;



	trace_amdgpu_cs_bo_status(list->num_entries, total_size);

	return 0;



error_free:

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+10 −5
Original line number Diff line number Diff line
@@ -312,6 +312,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device, 
		return RREG32_UVD_CTX(index);

	case CGS_IND_REG__DIDT:

		return RREG32_DIDT(index);

	case CGS_IND_REG_GC_CAC:

		return RREG32_GC_CAC(index);

	case CGS_IND_REG__AUDIO_ENDPT:

		DRM_ERROR("audio endpt register access not implemented.\n");

		return 0;
@@ -336,6 +338,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, 
		return WREG32_UVD_CTX(index, value);

	case CGS_IND_REG__DIDT:

		return WREG32_DIDT(index, value);

	case CGS_IND_REG_GC_CAC:

		return WREG32_GC_CAC(index, value);

	case CGS_IND_REG__AUDIO_ENDPT:

		DRM_ERROR("audio endpt register access not implemented.\n");

		return;
@@ -787,6 +791,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, 
		}



		hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;

		amdgpu_ucode_print_smc_hdr(&hdr->header);

		adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);

		ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);

		ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
@@ -830,6 +835,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 
	case CGS_SYSTEM_INFO_GFX_CU_INFO:

		sys_info->value = adev->gfx.cu_info.number;

		break;

	case CGS_SYSTEM_INFO_GFX_SE_INFO:

		sys_info->value = adev->gfx.config.max_shader_engines;

		break;

	default:

		return -ENODEV;

	}
@@ -972,11 +980,11 @@ static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device, 
				params->integer.value = argument->value;

				break;

			case ACPI_TYPE_STRING:

				params->string.length = argument->method_length;

				params->string.length = argument->data_length;

				params->string.pointer = argument->pointer;

				break;

			case ACPI_TYPE_BUFFER:

				params->buffer.length = argument->method_length;

				params->buffer.length = argument->data_length;

				params->buffer.pointer = argument->pointer;

				break;

			default:
@@ -1079,17 +1087,14 @@ int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device, 
	struct cgs_acpi_method_info info = {0};



	acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;

	acpi_input[0].method_length = sizeof(uint32_t);

	acpi_input[0].data_length = sizeof(uint32_t);

	acpi_input[0].value = acpi_function;



	acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;

	acpi_input[1].method_length = CGS_ACPI_MAX_BUFFER_SIZE;

	acpi_input[1].data_length = input_size;

	acpi_input[1].pointer = pinput;



	acpi_output.type = CGS_ACPI_TYPE_BUFFER;

	acpi_output.method_length = CGS_ACPI_MAX_BUFFER_SIZE;

	acpi_output.data_length = output_size;

	acpi_output.pointer = poutput;