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Commit 6f63405c authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini
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MIPS: uasm: Add r6 MUL encoding 



Add the R6 MUL instruction encoding for 3 operand signed multiply to
uasm so that KVM can use uasm for generating its entry point code at
runtime on R6.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 9f730a60

arch/mips/include/uapi/asm/inst.h

+44 −0
Original line number Diff line number Diff line
@@ -92,6 +92,50 @@ enum spec3_op { 
	rdhwr_op  = 0x3b

};



/*

 * Bits 10-6 minor opcode for r6 spec mult/div encodings

 */

enum mult_op {

	mult_mult_op = 0x0,

	mult_mul_op = 0x2,

	mult_muh_op = 0x3,

};

enum multu_op {

	multu_multu_op = 0x0,

	multu_mulu_op = 0x2,

	multu_muhu_op = 0x3,

};

enum div_op {

	div_div_op = 0x0,

	div_div6_op = 0x2,

	div_mod_op = 0x3,

};

enum divu_op {

	divu_divu_op = 0x0,

	divu_divu6_op = 0x2,

	divu_modu_op = 0x3,

};

enum dmult_op {

	dmult_dmult_op = 0x0,

	dmult_dmul_op = 0x2,

	dmult_dmuh_op = 0x3,

};

enum dmultu_op {

	dmultu_dmultu_op = 0x0,

	dmultu_dmulu_op = 0x2,

	dmultu_dmuhu_op = 0x3,

};

enum ddiv_op {

	ddiv_ddiv_op = 0x0,

	ddiv_ddiv6_op = 0x2,

	ddiv_dmod_op = 0x3,

};

enum ddivu_op {

	ddivu_ddivu_op = 0x0,

	ddivu_ddivu6_op = 0x2,

	ddivu_dmodu_op = 0x3,

};



/*

 * rt field of bcond opcodes.

 */

arch/mips/mm/uasm-mips.c

+4 −0
Original line number Diff line number Diff line
@@ -121,7 +121,11 @@ static struct insn insn_table[] = { 
	{ insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mthi,  M(spec_op, 0, 0, 0, 0, mthi_op), RS },

	{ insn_mtlo,  M(spec_op, 0, 0, 0, 0, mtlo_op), RS },

#ifndef CONFIG_CPU_MIPSR6

	{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},

#else

	{ insn_mul, M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},

#endif

	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),	RS | RT | UIMM },

	{ insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },

#ifndef CONFIG_CPU_MIPSR6