Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6f50c835 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs 



CM3 uses a 64-bit counter and compare registers so add support for
them in the GIC counter interrupt.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10648/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c3f57f02

drivers/irqchip/irq-mips-gic.c

+24 −9
Original line number Diff line number Diff line
@@ -140,6 +140,9 @@ cycle_t gic_read_count(void) 
{

	unsigned int hi, hi2, lo;



	if (mips_cm_is64)

		return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));



	do {

		hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));

		lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
@@ -162,11 +165,15 @@ unsigned int gic_get_count_width(void) 


void gic_write_compare(cycle_t cnt)

{

	if (mips_cm_is64) {

		gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);

	} else {

		gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),

					(int)(cnt >> 32));

		gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),

					(int)(cnt & 0xffffffff));

	}

}



void gic_write_cpu_compare(cycle_t cnt, int cpu)

{
@@ -174,11 +181,16 @@ void gic_write_cpu_compare(cycle_t cnt, int cpu) 


	local_irq_save(flags);



	gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);

	gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);



	if (mips_cm_is64) {

		gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);

	} else {

		gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),

					(int)(cnt >> 32));

		gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),

					(int)(cnt & 0xffffffff));

	}



	local_irq_restore(flags);

}
@@ -187,6 +199,9 @@ cycle_t gic_read_compare(void) 
{

	unsigned int hi, lo;



	if (mips_cm_is64)

		return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));



	hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));

	lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));

include/linux/irqchip/mips-gic.h

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 


/* Shared Global Counter */

#define GIC_SH_COUNTER_31_00_OFS	0x0010

/* 64-bit counter register for CM3 */

#define GIC_SH_COUNTER_OFS		GIC_SH_COUNTER_31_00_OFS

#define GIC_SH_COUNTER_63_32_OFS	0x0014

#define GIC_SH_REVISIONID_OFS		0x0020
@@ -104,6 +106,8 @@ 
#define GIC_VPE_WD_COUNT0_OFS		0x0094

#define GIC_VPE_WD_INITIAL0_OFS		0x0098

#define GIC_VPE_COMPARE_LO_OFS		0x00a0

/* 64-bit Compare register on CM3 */

#define GIC_VPE_COMPARE_OFS		GIC_VPE_COMPARE_LO_OFS

#define GIC_VPE_COMPARE_HI_OFS		0x00a4



#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS	0x0100