Commit 6f15c506 authored May 20, 2011 by Alex Deucher Committed by Dave Airlie May 22, 2011

drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices



If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>

parent d291767b

drivers/gpu/drm/radeon/atombios_crtc.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
		args.v3.ucPostDiv = post_div;
		args.v3.ucPpll = pll_id;
		args.v3.ucMiscInfo = (pll_id << 2);
		if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		args.v3.ucMiscInfo \|= PIXEL_CLOCK_MISC_REF_DIV_SRC;
		args.v3.ucTransmitterId = encoder_id;
		args.v3.ucEncoderMode = encoder_mode;
		break;