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Commit 6f085072 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Stephen Boyd
Browse files

clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant 



A clock branch consisting of a mux and divider with non-standard
divider values.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2d7884a7

drivers/clk/rockchip/clk.h

+20 −0
Original line number Diff line number Diff line
@@ -308,6 +308,26 @@ struct rockchip_clk_branch { 
		.gate_offset	= -1,				\

	}



#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\

				mw, mf, ds, dw, df, dt)		\

	{							\

		.id		= _id,				\

		.branch_type	= branch_composite,		\

		.name		= cname,			\

		.parent_names	= pnames,			\

		.num_parents	= ARRAY_SIZE(pnames),		\

		.flags		= f,				\

		.muxdiv_offset	= mo,				\

		.mux_shift	= ms,				\

		.mux_width	= mw,				\

		.mux_flags	= mf,				\

		.div_shift	= ds,				\

		.div_width	= dw,				\

		.div_flags	= df,				\

		.div_table	= dt,				\

		.gate_offset	= -1,				\

	}



#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\

	{							\

		.id		= _id,				\