Commit 6ed34648 authored Jan 02, 2015 by Felipe Balbi Committed by Thomas Gleixner Jul 22, 2015

irqchip: omap-intc: Improve IRQ handler



As it turns out the current IRQ number will *always* be available from
SIR register which renders the reads of PENDING registers as plain
unnecessary overhead.

In order to catch any situation where SIR reads as zero, we're adding
a WARN() to turn it into a very verbose error and users actually
report it.

With this patch average running time of omap_intc_handle_irq() reduced
from about 28.5us to 19.8us as measured by the kernel function
profiler.

Tested with BeagleBoneBlack Rev A5C.

Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Cc: Linux ARM Kernel Mailing List <linux-arm-kernel@lists.infradead.org>
Link: http://lkml.kernel.org/r/20150720204910.GH5394@saruman.tx.rr.com


Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

parent e10fc03c

drivers/irqchip/irq-omap-intc.c

+5 −30

Original line number	Diff line number	Diff line
		@@ -330,37 +330,12 @@ static int __init omap_init_irq(u32 base, struct device_node *node)
		static asmlinkage void __exception_irq_entry
		omap_intc_handle_irq(struct pt_regs *regs)
		{
		u32 irqnr = 0;
		int handled_irq = 0;
		int i;

		do {
		for (i = 0; i < omap_nr_pending; i++) {
		irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
		if (irqnr)
		goto out;
		}

		out:
		if (!irqnr)
		break;
		u32 irqnr;

		irqnr = intc_readl(INTC_SIR);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
		WARN_ONCE(!irqnr, "Spurious IRQ ?\n");
		handle_domain_irq(domain, irqnr, regs);
		handled_irq = 1;
		}
		} while (irqnr);

		/*
		* If an irq is masked or deasserted while active, we will
		* keep ending up here with no irq handled. So remove it from
		* the INTC with an ack.
		*/
		if (!handled_irq)
		omap_ack_irq(NULL);
		}

		void __init omap3_init_irq(void)