Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6eae43c5 authored by Gabor Juhos's avatar Gabor Juhos Committed by Ralf Baechle
Browse files

MIPS: ath79: add GPIOLIB support 



This patch implements generic GPIO routines for the built-in
GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs.

Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Signed-off-by: default avatarImre Kaloz <kaloz@openwrt.org>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: linux-mips@linux-mips.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Cc: Kathy Giori <Kathy.Giori@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1948/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d4a67d9d

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ config AR7 


config ATH79

	bool "Atheros AR71XX/AR724X/AR913X based boards"

	select ARCH_REQUIRE_GPIOLIB

	select BOOT_RAW

	select CEVT_R4K

	select CSRC_R4K

arch/mips/ath79/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 
# under the terms of the GNU General Public License version 2 as published

# by the Free Software Foundation.



obj-y	:= prom.o setup.o irq.o common.o clock.o

obj-y	:= prom.o setup.o irq.o common.o clock.o gpio.o



obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o

arch/mips/ath79/common.h

+5 −0
Original line number Diff line number Diff line
@@ -23,4 +23,9 @@ 
void ath79_clocks_init(void);

void ath79_ddr_wb_flush(unsigned int reg);



void ath79_gpio_function_enable(u32 mask);

void ath79_gpio_function_disable(u32 mask);

void ath79_gpio_function_setup(u32 set, u32 clear);

void ath79_gpio_init(void);



#endif /* __ATH79_COMMON_H */

arch/mips/ath79/gpio.c

0 → 100644
+197 −0
Original line number Diff line number Diff line 
/*

 *  Atheros AR71XX/AR724X/AR913X GPIO API support

 *

 *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>

 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/module.h>

#include <linux/types.h>

#include <linux/spinlock.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/gpio.h>



#include <asm/mach-ath79/ar71xx_regs.h>

#include <asm/mach-ath79/ath79.h>

#include "common.h"



static void __iomem *ath79_gpio_base;

static unsigned long ath79_gpio_count;

static DEFINE_SPINLOCK(ath79_gpio_lock);



static void __ath79_gpio_set_value(unsigned gpio, int value)

{

	void __iomem *base = ath79_gpio_base;



	if (value)

		__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);

	else

		__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);

}



static int __ath79_gpio_get_value(unsigned gpio)

{

	return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;

}



static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)

{

	return __ath79_gpio_get_value(offset);

}



static void ath79_gpio_set_value(struct gpio_chip *chip,

				  unsigned offset, int value)

{

	__ath79_gpio_set_value(offset, value);

}



static int ath79_gpio_direction_input(struct gpio_chip *chip,

				       unsigned offset)

{

	void __iomem *base = ath79_gpio_base;

	unsigned long flags;



	spin_lock_irqsave(&ath79_gpio_lock, flags);



	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),

		     base + AR71XX_GPIO_REG_OE);



	spin_unlock_irqrestore(&ath79_gpio_lock, flags);



	return 0;

}



static int ath79_gpio_direction_output(struct gpio_chip *chip,

					unsigned offset, int value)

{

	void __iomem *base = ath79_gpio_base;

	unsigned long flags;



	spin_lock_irqsave(&ath79_gpio_lock, flags);



	if (value)

		__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);

	else

		__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);



	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),

		     base + AR71XX_GPIO_REG_OE);



	spin_unlock_irqrestore(&ath79_gpio_lock, flags);



	return 0;

}



static struct gpio_chip ath79_gpio_chip = {

	.label			= "ath79",

	.get			= ath79_gpio_get_value,

	.set			= ath79_gpio_set_value,

	.direction_input	= ath79_gpio_direction_input,

	.direction_output	= ath79_gpio_direction_output,

	.base			= 0,

};



void ath79_gpio_function_enable(u32 mask)

{

	void __iomem *base = ath79_gpio_base;

	unsigned long flags;



	spin_lock_irqsave(&ath79_gpio_lock, flags);



	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,

		     base + AR71XX_GPIO_REG_FUNC);

	/* flush write */

	__raw_readl(base + AR71XX_GPIO_REG_FUNC);



	spin_unlock_irqrestore(&ath79_gpio_lock, flags);

}



void ath79_gpio_function_disable(u32 mask)

{

	void __iomem *base = ath79_gpio_base;

	unsigned long flags;



	spin_lock_irqsave(&ath79_gpio_lock, flags);



	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,

		     base + AR71XX_GPIO_REG_FUNC);

	/* flush write */

	__raw_readl(base + AR71XX_GPIO_REG_FUNC);



	spin_unlock_irqrestore(&ath79_gpio_lock, flags);

}



void ath79_gpio_function_setup(u32 set, u32 clear)

{

	void __iomem *base = ath79_gpio_base;

	unsigned long flags;



	spin_lock_irqsave(&ath79_gpio_lock, flags);



	__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,

		     base + AR71XX_GPIO_REG_FUNC);

	/* flush write */

	__raw_readl(base + AR71XX_GPIO_REG_FUNC);



	spin_unlock_irqrestore(&ath79_gpio_lock, flags);

}



void __init ath79_gpio_init(void)

{

	int err;



	if (soc_is_ar71xx())

		ath79_gpio_count = AR71XX_GPIO_COUNT;

	else if (soc_is_ar724x())

		ath79_gpio_count = AR724X_GPIO_COUNT;

	else if (soc_is_ar913x())

		ath79_gpio_count = AR913X_GPIO_COUNT;

	else

		BUG();



	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);

	ath79_gpio_chip.ngpio = ath79_gpio_count;



	err = gpiochip_add(&ath79_gpio_chip);

	if (err)

		panic("cannot add AR71xx GPIO chip, error=%d", err);

}



int gpio_get_value(unsigned gpio)

{

	if (gpio < ath79_gpio_count)

		return __ath79_gpio_get_value(gpio);



	return __gpio_get_value(gpio);

}

EXPORT_SYMBOL(gpio_get_value);



void gpio_set_value(unsigned gpio, int value)

{

	if (gpio < ath79_gpio_count)

		__ath79_gpio_set_value(gpio, value);

	else

		__gpio_set_value(gpio, value);

}

EXPORT_SYMBOL(gpio_set_value);



int gpio_to_irq(unsigned gpio)

{

	/* FIXME */

	return -EINVAL;

}

EXPORT_SYMBOL(gpio_to_irq);



int irq_to_gpio(unsigned irq)

{

	/* FIXME */

	return -EINVAL;

}

EXPORT_SYMBOL(irq_to_gpio);

arch/mips/ath79/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -157,7 +157,6 @@ void __init plat_mem_setup(void) 
					   AR71XX_RESET_SIZE);

	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,

					 AR71XX_PLL_SIZE);



	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,

					 AR71XX_DDR_CTRL_SIZE);
@@ -183,6 +182,7 @@ void __init plat_time_init(void) 


static int __init ath79_setup(void)

{

	ath79_gpio_init();

	ath79_register_uart();

	return 0;

}