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Commit 6e760c8d authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ca4973dd

arch/mips/Kconfig

+20 −6
Original line number Original line Diff line number Diff line
@@ -1050,14 +1050,28 @@ choice 
	prompt "CPU type"

	prompt "CPU type"

	default CPU_R4X00

	default CPU_R4X00





config CPU_MIPS32

config CPU_MIPS32_R1

	bool "MIPS32"

	bool "MIPS32 Release 1"

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_HAS_PREFETCH

	help

	  Choose this option to build a kernel for release 1 or later of the

	  MIPS32 architecture.  Most modern embedded systems with a 32-bit

	  MIPS processor are based on a MIPS32 processor.  If you know the

	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.





config CPU_MIPS64

config CPU_MIPS64_R1

	bool "MIPS64"

	bool "MIPS64 Release 1"

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_HAS_PREFETCH

	help

	  Choose this option to build a kernel for release 1 or later of the

	  MIPS64 architecture.  Many modern embedded systems with a 64-bit

	  MIPS processor are based on a MIPS64 processor.  If you know the

	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.





config CPU_R3000

config CPU_R3000

	bool "R3000"

	bool "R3000"
@@ -1253,7 +1267,7 @@ config SB1_PASS_2_1_WORKAROUNDS 




config 64BIT_PHYS_ADDR

config 64BIT_PHYS_ADDR

	bool "Support for 64-bit physical address space"

	bool "Support for 64-bit physical address space"

	depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT

	depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT





config CPU_ADVANCED

config CPU_ADVANCED

	bool "Override CPU Options"

	bool "Override CPU Options"
@@ -1276,7 +1290,7 @@ config CPU_HAS_LLSC 




config CPU_HAS_LLDSCD

config CPU_HAS_LLDSCD

	bool "lld/scd Instructions available" if CPU_ADVANCED

	bool "lld/scd Instructions available" if CPU_ADVANCED

	default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32

	default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1

	help

	help

	  Say Y here if your CPU has the lld and scd instructions, the 64-bit

	  Say Y here if your CPU has the lld and scd instructions, the 64-bit

	  equivalents of ll and sc.  Say Y here for better performance, N if

	  equivalents of ll and sc.  Say Y here for better performance, N if

arch/mips/Makefile

+2 −2
Original line number Original line Diff line number Diff line
@@ -182,11 +182,11 @@ cflags-$(CONFIG_CPU_TX49XX) += \ 
			$(call set_gccflags,r4600,mips3,r4600,mips3,mips2)  \

			$(call set_gccflags,r4600,mips3,r4600,mips3,mips2)  \

			-Wa,--trap

			-Wa,--trap





cflags-$(CONFIG_CPU_MIPS32)	+= \

cflags-$(CONFIG_CPU_MIPS32_R1)	+= \

			$(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \

			$(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \

			-Wa,--trap

			-Wa,--trap





cflags-$(CONFIG_CPU_MIPS64)	+= \

cflags-$(CONFIG_CPU_MIPS64_R1)	+= \

			$(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \

			$(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \

			-Wa,--trap

			-Wa,--trap

arch/mips/kernel/Makefile

+2 −2
Original line number Original line Diff line number Diff line
@@ -28,8 +28,8 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o 
obj-$(CONFIG_CPU_NEVADA)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_NEVADA)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_R10000)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_R10000)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_SB1)		+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_SB1)		+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_MIPS32)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_MIPS32_R1)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_MIPS64)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_MIPS64_R1)	+= r4k_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_R6000)		+= r6000_fpu.o r4k_switch.o

obj-$(CONFIG_CPU_R6000)		+= r6000_fpu.o r4k_switch.o





obj-$(CONFIG_SMP)		+= smp.o

obj-$(CONFIG_SMP)		+= smp.o

arch/mips/kernel/r4k_switch.S

+1 −1
Original line number Original line Diff line number Diff line
@@ -165,7 +165,7 @@ LEAF(_init_fpu) 
1:

1:

#endif

#endif





#ifdef CONFIG_CPU_MIPS32

#ifdef CONFIG_CPU_MIPS32_R1

	mtc1	t1, $f0

	mtc1	t1, $f0

	mtc1	t1, $f1

	mtc1	t1, $f1

	mtc1	t1, $f2

	mtc1	t1, $f2

arch/mips/kernel/traps.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -864,7 +864,7 @@ asmlinkage void cache_parity_error(void) 
	       reg_val & (1<<22) ? "E0 " : "");

	       reg_val & (1<<22) ? "E0 " : "");

	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));

	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));





#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)

#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)

	if (reg_val & (1<<22))

	if (reg_val & (1<<22))

		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());

		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());