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Commit 6df944c5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-gem-update' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-gem-update' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/i915: Return error in i915_gem_set_to_gtt_domain if we're not in the GTT.
  drm/i915: Retry execbuffer pinning after clearing the GTT
  drm/i915: Move the execbuffer domain computations together
  drm/i915: Rename object_set_domain to object_set_to_gpu_domain
  drm/i915: Make a single set-to-cpu-domain path and use it wherever needed.
  drm/i915: Make a single set-to-gtt-domain path.
  drm/i915: If interrupted while setting object domains, still emit the flush.
  drm/i915: Move flushing list cleanup from flush request retire to request emit.
  drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling.
parents 341e5580 02354392

drivers/gpu/drm/i915/i915_drv.h

+10 −5
Original line number Diff line number Diff line
@@ -244,6 +244,10 @@ typedef struct drm_i915_private { 
		 * List of objects currently involved in rendering from the

		 * ringbuffer.

		 *

		 * Includes buffers having the contents of their GPU caches

		 * flushed, not necessarily primitives.  last_rendering_seqno

		 * represents when the rendering involved will be completed.

		 *

		 * A reference is held on the buffer while on this list.

		 */

		struct list_head active_list;
@@ -253,6 +257,8 @@ typedef struct drm_i915_private { 
		 * still have a write_domain which needs to be flushed before

		 * unbinding.

		 *

		 * last_rendering_seqno is 0 while an object is in this list.

		 *

		 * A reference is held on the buffer while on this list.

		 */

		struct list_head flushing_list;
@@ -261,6 +267,8 @@ typedef struct drm_i915_private { 
		 * LRU list of objects which are not in the ringbuffer and

		 * are ready to unbind, but are still in the GTT.

		 *

		 * last_rendering_seqno is 0 while an object is in this list.

		 *

		 * A reference is not held on the buffer while on this list,

		 * as merely being GTT-bound shouldn't prevent its being

		 * freed, and we'll pull it off the list in the free path.
@@ -371,8 +379,8 @@ struct drm_i915_gem_object { 
	uint32_t agp_type;



	/**

	 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when

	 * GEM_DOMAIN_CPU is not in the object's read domain.

	 * If present, while GEM_DOMAIN_CPU is in the read domain this array

	 * flags which individual pages are valid.

	 */

	uint8_t *page_cpu_valid;

};
@@ -394,9 +402,6 @@ struct drm_i915_gem_request { 
	/** Time at which this request was emitted, in jiffies. */

	unsigned long emitted_jiffies;



	/** Cache domains that were flushed at the start of the request. */

	uint32_t flush_domains;



	struct list_head list;

};

drivers/gpu/drm/i915/i915_gem.c

+403 −234

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/i915_gem_proc.c

+2 −3
Original line number Diff line number Diff line
@@ -166,10 +166,9 @@ static int i915_gem_request_info(char *buf, char **start, off_t offset, 
	list_for_each_entry(gem_request, &dev_priv->mm.request_list,

			    list)

	{

		DRM_PROC_PRINT("    %d @ %d %08x\n",

		DRM_PROC_PRINT("    %d @ %d\n",

			       gem_request->seqno,

			       (int) (jiffies - gem_request->emitted_jiffies),

			       gem_request->flush_domains);

			       (int) (jiffies - gem_request->emitted_jiffies));

	}

	if (len > request + offset)

		return request;

drivers/gpu/drm/i915/i915_gem_tiling.c

+4 −3
Original line number Diff line number Diff line
@@ -119,9 +119,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
			    dcc & DCC_CHANNEL_XOR_DISABLE) {

				swizzle_x = I915_BIT_6_SWIZZLE_9_10;

				swizzle_y = I915_BIT_6_SWIZZLE_9;

			} else if (IS_I965GM(dev) || IS_GM45(dev)) {

				/* GM965 only does bit 11-based channel

				 * randomization

			} else if ((IS_I965GM(dev) || IS_GM45(dev)) &&

				   (dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {

				/* GM965/GM45 does either bit 11 or bit 17

				 * swizzling.

				 */

				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;

				swizzle_y = I915_BIT_6_SWIZZLE_9_11;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -522,6 +522,7 @@ 
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)

#define DCC_ADDRESSING_MODE_MASK			(3 << 0)

#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)

#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)



/** 965 MCH register controlling DRAM channel configuration */

#define C0DRB3			0x10206