Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 (6d7b9efa) · Commits · e / devices / android_kernel_teracube_2e

drivers/char/drm/i915_irq.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -202,10 +202,15 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
		void i915_driver_irq_uninstall(drm_device_t * dev)
		{
		drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
		u16 temp;

		if (!dev_priv)
		return;

		I915_WRITE16(I915REG_HWSTAM, 0xffff);
		I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
		I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);

		temp = I915_READ16(I915REG_INT_IDENTITY_R);
		I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
		}

drivers/char/drm/r300_cmdbuf.c

+48 −0

Original line number	Diff line number	Diff line
		@@ -161,6 +161,7 @@ void r300_init_reg_flags(void)
		ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
		ADD_RANGE(R300_GB_ENABLE, 1);
		ADD_RANGE(R300_GB_MSPOS0, 5);
		ADD_RANGE(R300_TX_CNTL, 1);
		ADD_RANGE(R300_TX_ENABLE, 1);
		ADD_RANGE(0x4200, 4);
		ADD_RANGE(0x4214, 1);
		@@ -489,6 +490,50 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,

		return 0;
		}
		static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
		drm_radeon_kcmd_buffer_t *cmdbuf)
		{
		u32 cmd = (u32 ) cmdbuf->buf;
		int count, ret;
		RING_LOCALS;

		count=(cmd[0]>>16) & 0x3fff;

		if (cmd[0] & 0x8000) {
		u32 offset;

		if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
		\| RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
		offset = cmd[2] << 10;
		ret = r300_check_offset(dev_priv, offset);
		if (ret) {
		DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
		return DRM_ERR(EINVAL);
		}
		}

		if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
		(cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
		offset = cmd[3] << 10;
		ret = r300_check_offset(dev_priv, offset);
		if (ret) {
		DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
		return DRM_ERR(EINVAL);
		}

		}
		}

		BEGIN_RING(count+2);
		OUT_RING(cmd[0]);
		OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
		ADVANCE_RING();

		cmdbuf->buf += (count+2)*4;
		cmdbuf->bufsz -= (count+2)*4;

		return 0;
		}

		static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
		drm_radeon_kcmd_buffer_t *cmdbuf)
		@@ -527,6 +572,9 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
		case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
		return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);

		case RADEON_CNTL_BITBLT_MULTI:
		return r300_emit_bitblt_multi(dev_priv, cmdbuf);

		case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
		case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
		case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */

drivers/char/drm/r300_reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -451,6 +451,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
		/* END */

		/* gap */
		/* Zero to flush caches. */
		#define R300_TX_CNTL 0x4100

		/* The upper enable bits are guessed, based on fglrx reported limits. */
		#define R300_TX_ENABLE 0x4104
		# define R300_TX_ENABLE_0 (1 << 0)

drivers/char/drm/radeon_drv.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -90,9 +90,10 @@
		* 1.19- Add support for gart table in FB memory and PCIE r300
		* 1.20- Add support for r300 texrect
		* 1.21- Add support for card type getparam
		* 1.22- Add support for texture cache flushes (R300_TX_CNTL)
		*/
		#define DRIVER_MAJOR 1
		#define DRIVER_MINOR 21
		#define DRIVER_MINOR 22
		#define DRIVER_PATCHLEVEL 0

		/*