Commit 6d3ec1ae authored Jan 25, 2012 by Catalin Marinas Committed by Russell King Feb 02, 2012

ARM: 7302/1: Add TLB flushing for both entries in a PMD

Linux uses two PMD entries for a PTE with the classic page table format,
covering 2MB range. However, the __pte_free_tlb() function only adds a
single TLB flush corresponding to 1MB range covering 'addr'. On
Cortex-A15, level 1 entries can be cached by the TLB independently of
the level 2 entries and without additional flushing a PMD entry would be
left pointing at the wrong PTE. The patch limits the TLB flushing range
to two 4KB pages around the 1MB boundary within PMD.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 91756acb

arch/arm/include/asm/tlb.h

+9 −1

Original line number	Diff line number	Diff line
		@@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
		unsigned long addr)
		{
		pgtable_page_dtor(pte);
		tlb_add_flush(tlb, addr);

		/*
		* With the classic ARM MMU, a pte page has two corresponding pmd
		* entries, each covering 1MB.
		*/
		addr &= PMD_MASK;
		tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
		tlb_add_flush(tlb, addr + SZ_1M);

		tlb_remove_page(tlb, pte);
		}