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Commit 6d3da018 authored by Antoine Tenart's avatar Antoine Tenart Committed by Sebastian Hesselbarth
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ARM: dts: berlin: add the BG2 GPIO nodes 



The Berlin BG2 has 32 GPIOs in SoC power domain and 16 in the SM one.
Only the first 8 SM GPIOs have interrupt support.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent cedf57fc

arch/arm/boot/dts/berlin2.dtsi

+105 −0
Original line number Diff line number Diff line
@@ -99,6 +99,78 @@ 
			ranges = <0 0xe80000 0x10000>;

			interrupt-parent = <&aic>;



			gpio0: gpio@0400 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0400 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porta: gpio-port@0 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <0>;

				};

			};



			gpio1: gpio@0800 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0800 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portb: gpio-port@1 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <1>;

				};

			};



			gpio2: gpio@0c00 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0c00 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portc: gpio-port@2 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <2>;

				};

			};



			gpio3: gpio@1000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x1000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portd: gpio-port@3 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <3>;

				};

			};



			timer0: timer@2c00 {

				compatible = "snps,dw-apb-timer";

				reg = <0x2c00 0x14>;
@@ -194,6 +266,39 @@ 
			ranges = <0 0xfc0000 0x10000>;

			interrupt-parent = <&sic>;



			sm_gpio1: gpio@5000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x5000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

				};

			};



			sm_gpio0: gpio@c000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0xc000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <8>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <11>;

				};

			};



			uart0: serial@9000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x9000 0x100>;