microblaze: Fix coding style issues (6bd55f0b) · Commits · e / devices / android_kernel_teracube_2e

arch/microblaze/include/asm/io.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -150,7 +150,7 @@ static inline void writel(unsigned int v, volatile void __iomem *addr)
	#define page_to_bus(page) (page_to_phys(page))		#define page_to_bus(page) (page_to_phys(page))
	#define bus_to_virt(addr) (phys_to_virt(addr))		#define bus_to_virt(addr) (phys_to_virt(addr))

	extern void iounmap(void *addr);		extern void iounmap(void __iomem *addr);
	/extern void __ioremap(phys_addr_t address, unsigned long size,		/extern void __ioremap(phys_addr_t address, unsigned long size,
	unsigned long flags);*/		unsigned long flags);*/
	extern void __iomem *ioremap(phys_addr_t address, unsigned long size);		extern void __iomem *ioremap(phys_addr_t address, unsigned long size);

arch/microblaze/kernel/cpu/cache.c

+68 −80

Original line number	Original line	Diff line number	Diff line
	@@ -17,82 +17,70 @@

	static inline void __enable_icache_msr(void)		static inline void __enable_icache_msr(void)
	{		{
	__asm__ __volatile__ (" msrset r0, %0; \		__asm__ __volatile__ (" msrset r0, %0;" \
	nop; " \		"nop;" \
	: : "i" (MSR_ICE) : "memory");		: : "i" (MSR_ICE) : "memory");
	}		}

	static inline void __disable_icache_msr(void)		static inline void __disable_icache_msr(void)
	{		{
	__asm__ __volatile__ (" msrclr r0, %0; \		__asm__ __volatile__ (" msrclr r0, %0;" \
	nop; " \		"nop;" \
	: : "i" (MSR_ICE) : "memory");		: : "i" (MSR_ICE) : "memory");
	}		}

	static inline void __enable_dcache_msr(void)		static inline void __enable_dcache_msr(void)
	{		{
	__asm__ __volatile__ (" msrset r0, %0; \		__asm__ __volatile__ (" msrset r0, %0;" \
	nop; " \		"nop;" \
	: \		: : "i" (MSR_DCE) : "memory");
	: "i" (MSR_DCE) \
	: "memory");
	}		}

	static inline void __disable_dcache_msr(void)		static inline void __disable_dcache_msr(void)
	{		{
	__asm__ __volatile__ (" msrclr r0, %0; \		__asm__ __volatile__ (" msrclr r0, %0;" \
	nop; " \		"nop; " \
	: \		: : "i" (MSR_DCE) : "memory");
	: "i" (MSR_DCE) \
	: "memory");
	}		}

	static inline void __enable_icache_nomsr(void)		static inline void __enable_icache_nomsr(void)
	{		{
	__asm__ __volatile__ (" mfs r12, rmsr; \		__asm__ __volatile__ (" mfs r12, rmsr;" \
	nop; \		"nop;" \
	ori r12, r12, %0; \		"ori r12, r12, %0;" \
	mts rmsr, r12; \		"mts rmsr, r12;" \
	nop; " \		"nop;" \
	: \		: : "i" (MSR_ICE) : "memory", "r12");
	: "i" (MSR_ICE) \
	: "memory", "r12");
	}		}

	static inline void __disable_icache_nomsr(void)		static inline void __disable_icache_nomsr(void)
	{		{
	__asm__ __volatile__ (" mfs r12, rmsr; \		__asm__ __volatile__ (" mfs r12, rmsr;" \
	nop; \		"nop;" \
	andi r12, r12, ~%0; \		"andi r12, r12, ~%0;" \
	mts rmsr, r12; \		"mts rmsr, r12;" \
	nop; " \		"nop;" \
	: \		: : "i" (MSR_ICE) : "memory", "r12");
	: "i" (MSR_ICE) \
	: "memory", "r12");
	}		}

	static inline void __enable_dcache_nomsr(void)		static inline void __enable_dcache_nomsr(void)
	{		{
	__asm__ __volatile__ (" mfs r12, rmsr; \		__asm__ __volatile__ (" mfs r12, rmsr;" \
	nop; \		"nop;" \
	ori r12, r12, %0; \		"ori r12, r12, %0;" \
	mts rmsr, r12; \		"mts rmsr, r12;" \
	nop; " \		"nop;" \
	: \		: : "i" (MSR_DCE) : "memory", "r12");
	: "i" (MSR_DCE) \
	: "memory", "r12");
	}		}

	static inline void __disable_dcache_nomsr(void)		static inline void __disable_dcache_nomsr(void)
	{		{
	__asm__ __volatile__ (" mfs r12, rmsr; \		__asm__ __volatile__ (" mfs r12, rmsr;" \
	nop; \		"nop;" \
	andi r12, r12, ~%0; \		"andi r12, r12, ~%0;" \
	mts rmsr, r12; \		"mts rmsr, r12;" \
	nop; " \		"nop;" \
	: \		: : "i" (MSR_DCE) : "memory", "r12");
	: "i" (MSR_DCE) \
	: "memory", "r12");
	}		}


	@@ -106,7 +94,7 @@ do { \
	int align = ~(cache_line_length - 1); \		int align = ~(cache_line_length - 1); \
	end = min(start + cache_size, end); \		end = min(start + cache_size, end); \
	start &= align; \		start &= align; \
	} while (0);		} while (0)

	/*		/*
	* Helper macro to loop over the specified cache_size/line_length and		* Helper macro to loop over the specified cache_size/line_length and
	@@ -118,12 +106,12 @@ do { \
	int step = -line_length; \		int step = -line_length; \
	WARN_ON(step >= 0); \		WARN_ON(step >= 0); \
	\		\
	__asm__ __volatile__ (" 1: " #op " %0, r0; \		__asm__ __volatile__ (" 1: " #op " %0, r0;" \
	bgtid %0, 1b; \		"bgtid %0, 1b;" \
	addk %0, %0, %1; \		"addk %0, %0, %1;" \
	" : : "r" (len), "r" (step) \		: : "r" (len), "r" (step) \
	: "memory"); \		: "memory"); \
	} while (0);		} while (0)

	/* Used for wdc.flush/clear which can use rB for offset which is not possible		/* Used for wdc.flush/clear which can use rB for offset which is not possible
	* to use for simple wdc or wic.		* to use for simple wdc or wic.
	@@ -142,12 +130,12 @@ do { \
	count = end - start; \		count = end - start; \
	WARN_ON(count < 0); \		WARN_ON(count < 0); \
	\		\
	__asm__ __volatile__ (" 1: " #op " %0, %1; \		__asm__ __volatile__ (" 1: " #op " %0, %1;" \
	bgtid %1, 1b; \		"bgtid %1, 1b;" \
	addk %1, %1, %2; \		"addk %1, %1, %2;" \
	" : : "r" (start), "r" (count), \		: : "r" (start), "r" (count), \
	"r" (step) : "memory"); \		"r" (step) : "memory"); \
	} while (0);		} while (0)

	/* It is used only first parameter for OP - for wic, wdc */		/* It is used only first parameter for OP - for wic, wdc */
	#define CACHE_RANGE_LOOP_1(start, end, line_length, op) \		#define CACHE_RANGE_LOOP_1(start, end, line_length, op) \
	@@ -157,13 +145,13 @@ do { \
	end = ((end & align) == end) ? end - line_length : end & align; \		end = ((end & align) == end) ? end - line_length : end & align; \
	WARN_ON(end - start < 0); \		WARN_ON(end - start < 0); \
	\		\
	__asm__ __volatile__ (" 1: " #op " %1, r0; \		__asm__ __volatile__ (" 1: " #op " %1, r0;" \
	cmpu %0, %1, %2; \		"cmpu %0, %1, %2;" \
	bgtid %0, 1b; \		"bgtid %0, 1b;" \
	addk %1, %1, %3; \		"addk %1, %1, %3;" \
	" : : "r" (temp), "r" (start), "r" (end),\		: : "r" (temp), "r" (start), "r" (end), \
	"r" (line_length) : "memory"); \		"r" (line_length) : "memory"); \
	} while (0);		} while (0)

	#define ASM_LOOP		#define ASM_LOOP

	@@ -352,7 +340,7 @@ static void __invalidate_dcache_all_noirq_wt(void)
	#endif		#endif
	pr_debug("%s\n", __func__);		pr_debug("%s\n", __func__);
	#ifdef ASM_LOOP		#ifdef ASM_LOOP
	CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc)		CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
	#else		#else
	for (i = 0; i < cpuinfo.dcache_size;		for (i = 0; i < cpuinfo.dcache_size;
	i += cpuinfo.dcache_line_length)		i += cpuinfo.dcache_line_length)
	@@ -361,7 +349,8 @@ static void __invalidate_dcache_all_noirq_wt(void)
	#endif		#endif
	}		}

	/* FIXME It is blindly invalidation as is expected		/*
			* FIXME It is blindly invalidation as is expected
	* but can't be called on noMMU in microblaze_cache_init below		* but can't be called on noMMU in microblaze_cache_init below
	*		*
	* MS: noMMU kernel won't boot if simple wdc is used		* MS: noMMU kernel won't boot if simple wdc is used
	@@ -375,7 +364,7 @@ static void __invalidate_dcache_all_wb(void)
	pr_debug("%s\n", __func__);		pr_debug("%s\n", __func__);
	#ifdef ASM_LOOP		#ifdef ASM_LOOP
	CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,		CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
	wdc)		wdc);
	#else		#else
	for (i = 0; i < cpuinfo.dcache_size;		for (i = 0; i < cpuinfo.dcache_size;
	i += cpuinfo.dcache_line_length)		i += cpuinfo.dcache_line_length)
	@@ -616,46 +605,45 @@ static const struct scache wt_nomsr_noirq = {
	#define CPUVER_7_20_A 0x0c		#define CPUVER_7_20_A 0x0c
	#define CPUVER_7_20_D 0x0f		#define CPUVER_7_20_D 0x0f

	#define INFO(s) printk(KERN_INFO "cache: " s "\n");

	void microblaze_cache_init(void)		void microblaze_cache_init(void)
	{		{
	if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {		if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {
	if (cpuinfo.dcache_wb) {		if (cpuinfo.dcache_wb) {
	INFO("wb_msr");		pr_info("wb_msr\n");
	mbc = (struct scache *)&wb_msr;		mbc = (struct scache *)&wb_msr;
	if (cpuinfo.ver_code <= CPUVER_7_20_D) {		if (cpuinfo.ver_code <= CPUVER_7_20_D) {
	/* MS: problem with signal handling - hw bug */		/* MS: problem with signal handling - hw bug */
	INFO("WB won't work properly");		pr_info("WB won't work properly\n");
	}		}
	} else {		} else {
	if (cpuinfo.ver_code >= CPUVER_7_20_A) {		if (cpuinfo.ver_code >= CPUVER_7_20_A) {
	INFO("wt_msr_noirq");		pr_info("wt_msr_noirq\n");
	mbc = (struct scache *)&wt_msr_noirq;		mbc = (struct scache *)&wt_msr_noirq;
	} else {		} else {
	INFO("wt_msr");		pr_info("wt_msr\n");
	mbc = (struct scache *)&wt_msr;		mbc = (struct scache *)&wt_msr;
	}		}
	}		}
	} else {		} else {
	if (cpuinfo.dcache_wb) {		if (cpuinfo.dcache_wb) {
	INFO("wb_nomsr");		pr_info("wb_nomsr\n");
	mbc = (struct scache *)&wb_nomsr;		mbc = (struct scache *)&wb_nomsr;
	if (cpuinfo.ver_code <= CPUVER_7_20_D) {		if (cpuinfo.ver_code <= CPUVER_7_20_D) {
	/* MS: problem with signal handling - hw bug */		/* MS: problem with signal handling - hw bug */
	INFO("WB won't work properly");		pr_info("WB won't work properly\n");
	}		}
	} else {		} else {
	if (cpuinfo.ver_code >= CPUVER_7_20_A) {		if (cpuinfo.ver_code >= CPUVER_7_20_A) {
	INFO("wt_nomsr_noirq");		pr_info("wt_nomsr_noirq\n");
	mbc = (struct scache *)&wt_nomsr_noirq;		mbc = (struct scache *)&wt_nomsr_noirq;
	} else {		} else {
	INFO("wt_nomsr");		pr_info("wt_nomsr\n");
	mbc = (struct scache *)&wt_nomsr;		mbc = (struct scache *)&wt_nomsr;
	}		}
	}		}
	}		}
	/* FIXME Invalidation is done in U-BOOT		/*
			* FIXME Invalidation is done in U-BOOT
	* WT cache: Data is already written to main memory		* WT cache: Data is already written to main memory
	* WB cache: Discard data on noMMU which caused that kernel doesn't boot		* WB cache: Discard data on noMMU which caused that kernel doesn't boot
	*/		*/

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

+10 −11

Original line number	Original line	Diff line number	Diff line
	@@ -27,7 +27,7 @@
	early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");		early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");
	#else		#else
	#define err_printk(x) \		#define err_printk(x) \
	printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n");		pr_info("ERROR: Microblaze " x "-different for PVR and DTS\n");
	#endif		#endif

	void set_cpuinfo_pvr_full(struct cpuinfo ci, struct device_node cpu)		void set_cpuinfo_pvr_full(struct cpuinfo ci, struct device_node cpu)
	@@ -38,12 +38,11 @@ void set_cpuinfo_pvr_full(struct cpuinfo ci, struct device_node cpu)

	CI(ver_code, VERSION);		CI(ver_code, VERSION);
	if (!ci->ver_code) {		if (!ci->ver_code) {
	printk(KERN_ERR "ERROR: MB has broken PVR regs "		pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n");
	"-> use DTS setting\n");
	return;		return;
	}		}

	temp = PVR_USE_BARREL(pvr) \| PVR_USE_MSR_INSTR(pvr) \|\		temp = PVR_USE_BARREL(pvr) \| PVR_USE_MSR_INSTR(pvr) \|
	PVR_USE_PCMP_INSTR(pvr) \| PVR_USE_DIV(pvr);		PVR_USE_PCMP_INSTR(pvr) \| PVR_USE_DIV(pvr);
	if (ci->use_instr != temp)		if (ci->use_instr != temp)
	err_printk("BARREL, MSR, PCMP or DIV");		err_printk("BARREL, MSR, PCMP or DIV");
	@@ -59,13 +58,13 @@ void set_cpuinfo_pvr_full(struct cpuinfo ci, struct device_node cpu)
	err_printk("HW_FPU");		err_printk("HW_FPU");
	ci->use_fpu = temp;		ci->use_fpu = temp;

	ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) \|\		ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) \|
	PVR_UNALIGNED_EXCEPTION(pvr) \|\		PVR_UNALIGNED_EXCEPTION(pvr) \|
	PVR_ILL_OPCODE_EXCEPTION(pvr) \|\		PVR_ILL_OPCODE_EXCEPTION(pvr) \|
	PVR_IOPB_BUS_EXCEPTION(pvr) \|\		PVR_IOPB_BUS_EXCEPTION(pvr) \|
	PVR_DOPB_BUS_EXCEPTION(pvr) \|\		PVR_DOPB_BUS_EXCEPTION(pvr) \|
	PVR_DIV_ZERO_EXCEPTION(pvr) \|\		PVR_DIV_ZERO_EXCEPTION(pvr) \|
	PVR_FPU_EXCEPTION(pvr) \|\		PVR_FPU_EXCEPTION(pvr) \|
	PVR_FSL_EXCEPTION(pvr);		PVR_FSL_EXCEPTION(pvr);

	CI(pvr_user1, USER1);		CI(pvr_user1, USER1);

arch/microblaze/kernel/cpu/cpuinfo.c

+6 −7

Original line number	Original line	Diff line number	Diff line
	@@ -68,31 +68,30 @@ void __init setup_cpuinfo(void)

	cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");		cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");
	if (!cpu)		if (!cpu)
	printk(KERN_ERR "You don't have cpu!!!\n");		pr_err("You don't have cpu!!!\n");

	printk(KERN_INFO "%s: initialising\n", __func__);		pr_info("%s: initialising\n", __func__);

	switch (cpu_has_pvr()) {		switch (cpu_has_pvr()) {
	case 0:		case 0:
	printk(KERN_WARNING		pr_warn("%s: No PVR support. Using static CPU info from FDT\n",
	"%s: No PVR support. Using static CPU info from FDT\n",
	__func__);		__func__);
	set_cpuinfo_static(&cpuinfo, cpu);		set_cpuinfo_static(&cpuinfo, cpu);
	break;		break;
	/* FIXME I found weird behavior with MB 7.00.a/b 7.10.a		/* FIXME I found weird behavior with MB 7.00.a/b 7.10.a
	* please do not use FULL PVR with MMU */		* please do not use FULL PVR with MMU */
	case 1:		case 1:
	printk(KERN_INFO "%s: Using full CPU PVR support\n",		pr_info("%s: Using full CPU PVR support\n",
	__func__);		__func__);
	set_cpuinfo_static(&cpuinfo, cpu);		set_cpuinfo_static(&cpuinfo, cpu);
	set_cpuinfo_pvr_full(&cpuinfo, cpu);		set_cpuinfo_pvr_full(&cpuinfo, cpu);
	break;		break;
	default:		default:
	printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);		pr_warn("%s: Unsupported PVR setting\n", __func__);
	set_cpuinfo_static(&cpuinfo, cpu);		set_cpuinfo_static(&cpuinfo, cpu);
	}		}

	if (cpuinfo.mmu_privins)		if (cpuinfo.mmu_privins)
	printk(KERN_WARNING "%s: Stream instructions enabled"		pr_warn("%s: Stream instructions enabled"
	" - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);		" - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);
	}		}

arch/microblaze/kernel/dma.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -11,7 +11,7 @@
	#include <linux/gfp.h>		#include <linux/gfp.h>
	#include <linux/dma-debug.h>		#include <linux/dma-debug.h>
	#include <linux/export.h>		#include <linux/export.h>
	#include <asm/bug.h>		#include <linux/bug.h>

	/*		/*
	* Generic direct DMA implementation		* Generic direct DMA implementation