Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6ba60b89 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: stop using the ring index in the SA 



The ring index will always collide as hash into the fence list, so use
the context number instead. That can still cause collisions, but they
are less likely than using ring indices.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4247c50

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −1
Original line number Diff line number Diff line
@@ -578,11 +578,14 @@ int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 
 * Assumption is that there won't be hole (all object on same

 * alignment).

 */



#define AMDGPU_SA_NUM_FENCE_LISTS	32



struct amdgpu_sa_manager {

	wait_queue_head_t	wq;

	struct amdgpu_bo	*bo;

	struct list_head	*hole;

	struct list_head	flist[AMDGPU_MAX_RINGS];

	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];

	struct list_head	olist;

	unsigned		size;

	uint64_t		gpu_addr;

drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c

+18 −35
Original line number Diff line number Diff line
@@ -60,9 +60,8 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 
	sa_manager->align = align;

	sa_manager->hole = &sa_manager->olist;

	INIT_LIST_HEAD(&sa_manager->olist);

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)

		INIT_LIST_HEAD(&sa_manager->flist[i]);

	}



	r = amdgpu_bo_create(adev, size, align, true, domain,

			     0, NULL, NULL, &sa_manager->bo);
@@ -228,11 +227,9 @@ static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager, 
	unsigned soffset, eoffset, wasted;

	int i;



	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

		if (!list_empty(&sa_manager->flist[i])) {

	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)

		if (!list_empty(&sa_manager->flist[i]))

			return true;

		}

	}



	soffset = amdgpu_sa_bo_hole_soffset(sa_manager);

	eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
@@ -265,12 +262,11 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, 
	/* go over all fence list and try to find the closest sa_bo

	 * of the current last

	 */

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {

		struct amdgpu_sa_bo *sa_bo;



		if (list_empty(&sa_manager->flist[i])) {

		if (list_empty(&sa_manager->flist[i]))

			continue;

		}



		sa_bo = list_first_entry(&sa_manager->flist[i],

					 struct amdgpu_sa_bo, flist);
@@ -299,7 +295,9 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, 
	}



	if (best_bo) {

		uint32_t idx = amdgpu_ring_from_fence(best_bo->fence)->idx;

		uint32_t idx = best_bo->fence->context;



		idx %= AMDGPU_SA_NUM_FENCE_LISTS;

		++tries[idx];

		sa_manager->hole = best_bo->olist.prev;
@@ -315,8 +313,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 
		     struct amdgpu_sa_bo **sa_bo,

		     unsigned size, unsigned align)

{

	struct fence *fences[AMDGPU_MAX_RINGS];

	unsigned tries[AMDGPU_MAX_RINGS];

	struct fence *fences[AMDGPU_SA_NUM_FENCE_LISTS];

	unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS];

	unsigned count;

	int i, r;

	signed long t;
@@ -338,7 +336,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 


	spin_lock(&sa_manager->wq.lock);

	do {

		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {

		for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {

			fences[i] = NULL;

			tries[i] = 0;

		}
@@ -355,7 +353,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 
			/* see if we can skip over some allocations */

		} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));



		for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)

		for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)

			if (fences[i])

				fences[count++] = fences[i];
@@ -394,8 +392,9 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, 
	spin_lock(&sa_manager->wq.lock);

	if (fence && !fence_is_signaled(fence)) {

		uint32_t idx;



		(*sa_bo)->fence = fence_get(fence);

		idx = amdgpu_ring_from_fence(fence)->idx;

		idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS;

		list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);

	} else {

		amdgpu_sa_bo_remove_locked(*sa_bo);
@@ -407,25 +406,6 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, 


#if defined(CONFIG_DEBUG_FS)



static void amdgpu_sa_bo_dump_fence(struct fence *fence, struct seq_file *m)

{

	struct amdgpu_fence *a_fence = to_amdgpu_fence(fence);

	struct amd_sched_fence *s_fence = to_amd_sched_fence(fence);



	if (a_fence)

		seq_printf(m, " protected by 0x%016llx on ring %d",

			   a_fence->seq, a_fence->ring->idx);



	if (s_fence) {

		struct amdgpu_ring *ring;





		ring = container_of(s_fence->sched, struct amdgpu_ring, sched);

		seq_printf(m, " protected by 0x%016x on ring %d",

			   s_fence->base.seqno, ring->idx);

	}

}



void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,

				  struct seq_file *m)

{
@@ -442,8 +422,11 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 
		}

		seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",

			   soffset, eoffset, eoffset - soffset);



		if (i->fence)

			amdgpu_sa_bo_dump_fence(i->fence, m);

			seq_printf(m, " protected by 0x%08x on context %d",

				   i->fence->seqno, i->fence->context);



		seq_printf(m, "\n");

	}

	spin_unlock(&sa_manager->wq.lock);