Merge branch 'amd-xgbe-next'

   - SerDes integration registers (1/2)

   - SerDes integration registers (2/2)

Optional properties:

- amd,speed-set: Speed capabilities of the device

    0 - 1GbE and 10GbE (default)

    1 - 2.5GbE and 10GbE

Example:

	xgbe_phy@e1240800 {

		compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45";

		reg = <0 0xe1240800 0 0x00400>,

		      <0 0xe1250000 0 0x00060>,

		      <0 0xe1250080 0 0x00004>;

		amd,speed-set = <0>;

	};

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the amd-xgbe interrupt

- clocks: Should be the DMA clock for the amd-xgbe device (used for

  calculating the correct Rx interrupt watchdog timer value on a DMA

  channel for coalescing)

- clock-names: Should be the name of the DMA clock, "dma_clk"

- clocks:

   - DMA clock for the amd-xgbe device (used for calculating the

     correct Rx interrupt watchdog timer value on a DMA channel

     for coalescing)

   - PTP clock for the amd-xgbe device

- clock-names: Should be the names of the clocks

   - "dma_clk" for the DMA clock

   - "ptp_clk" for the PTP clock

- phy-handle: See ethernet.txt file in the same directory

- phy-mode: See ethernet.txt file in the same directory

Optional properties:

- mac-address: mac address to be assigned to the device. Can be overridden

  by UEFI.

- dma-coherent: Present if dma operations are coherent

Example:

	xgbe@e0700000 {

		      <0 0xe0780000 0 0x80000>;

		interrupt-parent = <&gic>;

		interrupts = <0 325 4>;

		clocks = <&xgbe_clk>;

		clock-names = "dma_clk";

		clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;

		clock-names = "dma_clk", "ptp_clk";

		phy-handle = <&phy>;

		phy-mode = "xgmii";

		mac-address = [ 02 a1 a2 a3 a4 a5 ];

	select AMD_XGBE_PHY

	select BITREVERSE

	select CRC32

	select PTP_1588_CLOCK

	---help---

	  This driver supports the AMD 10GbE Ethernet device found on an

	  AMD SoC.

	  To compile this driver as a module, choose M here: the module

	  will be called amd-xgbe.

config AMD_XGBE_DCB

	bool "Data Center Bridging (DCB) support"

	default n

	depends on AMD_XGBE && DCB

	---help---

	  Say Y here to enable Data Center Bridging (DCB) support in the

	  driver.

	  If unsure, say N.

endif # NET_VENDOR_AMD

obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o

amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \

		 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o

		 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \

		 xgbe-ptp.o

amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o

amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o

#define MAC_MACA0LR			0x0304

#define MAC_MACA1HR			0x0308

#define MAC_MACA1LR			0x030c

#define MAC_TSCR			0x0d00

#define MAC_SSIR			0x0d04

#define MAC_STSR			0x0d08

#define MAC_STNR			0x0d0c

#define MAC_STSUR			0x0d10

#define MAC_STNUR			0x0d14

#define MAC_TSAR			0x0d18

#define MAC_TSSR			0x0d20

#define MAC_TXSNR			0x0d30

#define MAC_TXSSR			0x0d34

#define MAC_QTFCR_INC			4

#define MAC_MACA_INC			4

#define MAC_HTR_INC			4

#define MAC_RQC2_INC			4

#define MAC_RQC2_Q_PER_REG		4

/* MAC register entry bit positions and sizes */

#define MAC_HWF0R_ADDMACADRSEL_INDEX	18

#define MAC_HWF0R_ADDMACADRSEL_WIDTH	5

#define MAC_HWF1R_HASHTBLSZ_WIDTH	3

#define MAC_HWF1R_L3L4FNUM_INDEX	27

#define MAC_HWF1R_L3L4FNUM_WIDTH	4

#define MAC_HWF1R_NUMTC_INDEX		21

#define MAC_HWF1R_NUMTC_WIDTH		3

#define MAC_HWF1R_RSSEN_INDEX		20

#define MAC_HWF1R_RSSEN_WIDTH		1

#define MAC_HWF1R_RXFIFOSIZE_INDEX	0

#define MAC_HWF2R_TXCHCNT_WIDTH		4

#define MAC_HWF2R_TXQCNT_INDEX		6

#define MAC_HWF2R_TXQCNT_WIDTH		4

#define MAC_IER_TSIE_INDEX		12

#define MAC_IER_TSIE_WIDTH		1

#define MAC_ISR_MMCRXIS_INDEX		9

#define MAC_ISR_MMCRXIS_WIDTH		1

#define MAC_ISR_MMCTXIS_INDEX		10

#define MAC_ISR_MMCTXIS_WIDTH		1

#define MAC_ISR_PMTIS_INDEX		4

#define MAC_ISR_PMTIS_WIDTH		1

#define MAC_ISR_TSIS_INDEX		12

#define MAC_ISR_TSIS_WIDTH		1

#define MAC_MACA1HR_AE_INDEX		31

#define MAC_MACA1HR_AE_WIDTH		1

#define MAC_PFR_HMC_INDEX		2

#define MAC_RCR_LM_WIDTH		1

#define MAC_RCR_RE_INDEX		0

#define MAC_RCR_RE_WIDTH		1

#define MAC_RFCR_PFCE_INDEX		8

#define MAC_RFCR_PFCE_WIDTH		1

#define MAC_RFCR_RFE_INDEX		0

#define MAC_RFCR_RFE_WIDTH		1

#define MAC_RFCR_UP_INDEX		1

#define MAC_RFCR_UP_WIDTH		1

#define MAC_RQC0R_RXQ0EN_INDEX		0

#define MAC_RQC0R_RXQ0EN_WIDTH		2

#define MAC_SSIR_SNSINC_INDEX		8

#define MAC_SSIR_SNSINC_WIDTH		8

#define MAC_SSIR_SSINC_INDEX		16

#define MAC_SSIR_SSINC_WIDTH		8

#define MAC_TCR_SS_INDEX		29

#define MAC_TCR_SS_WIDTH		2

#define MAC_TCR_TE_INDEX		0

#define MAC_TCR_TE_WIDTH		1

#define MAC_TSCR_AV8021ASMEN_INDEX	28

#define MAC_TSCR_AV8021ASMEN_WIDTH	1

#define MAC_TSCR_SNAPTYPSEL_INDEX	16

#define MAC_TSCR_SNAPTYPSEL_WIDTH	2

#define MAC_TSCR_TSADDREG_INDEX		5

#define MAC_TSCR_TSADDREG_WIDTH		1

#define MAC_TSCR_TSCFUPDT_INDEX		1

#define MAC_TSCR_TSCFUPDT_WIDTH		1

#define MAC_TSCR_TSCTRLSSR_INDEX	9

#define MAC_TSCR_TSCTRLSSR_WIDTH	1

#define MAC_TSCR_TSENA_INDEX		0

#define MAC_TSCR_TSENA_WIDTH		1

#define MAC_TSCR_TSENALL_INDEX		8

#define MAC_TSCR_TSENALL_WIDTH		1

#define MAC_TSCR_TSEVNTENA_INDEX	14

#define MAC_TSCR_TSEVNTENA_WIDTH	1

#define MAC_TSCR_TSINIT_INDEX		2

#define MAC_TSCR_TSINIT_WIDTH		1

#define MAC_TSCR_TSIPENA_INDEX		11

#define MAC_TSCR_TSIPENA_WIDTH		1

#define MAC_TSCR_TSIPV4ENA_INDEX	13

#define MAC_TSCR_TSIPV4ENA_WIDTH	1

#define MAC_TSCR_TSIPV6ENA_INDEX	12

#define MAC_TSCR_TSIPV6ENA_WIDTH	1

#define MAC_TSCR_TSMSTRENA_INDEX	15

#define MAC_TSCR_TSMSTRENA_WIDTH	1

#define MAC_TSCR_TSVER2ENA_INDEX	10

#define MAC_TSCR_TSVER2ENA_WIDTH	1

#define MAC_TSCR_TXTSSTSM_INDEX		24

#define MAC_TSCR_TXTSSTSM_WIDTH		1

#define MAC_TSSR_TXTSC_INDEX		15

#define MAC_TSSR_TXTSC_WIDTH		1

#define MAC_TXSNR_TXTSSTSMIS_INDEX	31

#define MAC_TXSNR_TXTSSTSMIS_WIDTH	1

#define MAC_VLANHTR_VLHT_INDEX		0

#define MAC_VLANHTR_VLHT_WIDTH		16

#define MAC_VLANIR_VLTI_INDEX		20

#define MTL_RQDCM_INC			4

#define MTL_RQDCM_Q_PER_REG		4

#define MTL_TCPM_INC			4

#define MTL_TCPM_TC_PER_REG		4

/* MTL register entry bit positions and sizes */

#define MTL_OMR_ETSALG_INDEX		5

#define MTL_Q_TQOMR			0x00

#define MTL_Q_TQUR			0x04

#define MTL_Q_TQDR			0x08

#define MTL_Q_TCECR			0x10

#define MTL_Q_TCESR			0x14

#define MTL_Q_TCQWR			0x18

#define MTL_Q_RQOMR			0x40

#define MTL_Q_RQMPOCR			0x44

#define MTL_Q_RQDR			0x4c

#define MTL_Q_ISR			0x74

/* MTL queue register entry bit positions and sizes */

#define MTL_Q_TCQWR_QW_INDEX		0

#define MTL_Q_TCQWR_QW_WIDTH		21

#define MTL_Q_RQOMR_EHFC_INDEX		7

#define MTL_Q_RQOMR_EHFC_WIDTH		1

#define MTL_Q_RQOMR_RFA_INDEX		8

#define MTL_Q_RQOMR_RTC_WIDTH		2

#define MTL_Q_TQOMR_FTQ_INDEX		0

#define MTL_Q_TQOMR_FTQ_WIDTH		1

#define MTL_Q_TQOMR_Q2TCMAP_INDEX	8

#define MTL_Q_TQOMR_Q2TCMAP_WIDTH	3

#define MTL_Q_TQOMR_TQS_INDEX		16

#define MTL_Q_TQOMR_TQS_WIDTH		10

#define MTL_Q_TQOMR_TSF_INDEX		1

#define MTL_TC_INC			MTL_Q_INC

#define MTL_TC_ETSCR			0x10

#define MTL_TC_ETSSR			0x14

#define MTL_TC_QWR			0x18

/* MTL traffic class register entry bit positions and sizes */

#define MTL_TC_ETSCR_TSA_INDEX		0

#define MTL_TC_ETSCR_TSA_WIDTH		2

#define MTL_TC_QWR_QW_INDEX		0

#define MTL_TC_QWR_QW_WIDTH		21

/* MTL traffic class register value */

#define MTL_TSA_SP			0x00

#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1

#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX	2

#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH	1

#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX	3

#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH	1

#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX	4

#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH	1

#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX	5

#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH	1

#define RX_NORMAL_DESC0_OVT_INDEX		0

#define RX_NORMAL_DESC0_OVT_WIDTH		16

#define RX_NORMAL_DESC3_CDA_INDEX		27

#define RX_NORMAL_DESC3_CDA_WIDTH		1

#define RX_NORMAL_DESC3_CTXT_INDEX		30

#define RX_NORMAL_DESC3_CTXT_WIDTH		1

#define RX_NORMAL_DESC3_ES_INDEX		15

#define RX_NORMAL_DESC3_ES_WIDTH		1

#define RX_NORMAL_DESC3_ETLT_INDEX		16

#define RX_NORMAL_DESC3_PL_INDEX		0

#define RX_NORMAL_DESC3_PL_WIDTH		14

#define RX_CONTEXT_DESC3_TSA_INDEX		4

#define RX_CONTEXT_DESC3_TSA_WIDTH		1

#define RX_CONTEXT_DESC3_TSD_INDEX		6

#define RX_CONTEXT_DESC3_TSD_WIDTH		1

#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX	0

#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH	1

#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX	1

#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH	1

#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	2

#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1

#define TX_PACKET_ATTRIBUTES_PTP_INDEX		3

#define TX_PACKET_ATTRIBUTES_PTP_WIDTH		1

#define TX_CONTEXT_DESC2_MSS_INDEX		0

#define TX_CONTEXT_DESC2_MSS_WIDTH		15

#define TX_NORMAL_DESC2_HL_B1L_WIDTH		14

#define TX_NORMAL_DESC2_IC_INDEX		31

#define TX_NORMAL_DESC2_IC_WIDTH		1

#define TX_NORMAL_DESC2_TTSE_INDEX		30

#define TX_NORMAL_DESC2_TTSE_WIDTH		1

#define TX_NORMAL_DESC2_VTIR_INDEX		14

#define TX_NORMAL_DESC2_VTIR_WIDTH		2

#define TX_NORMAL_DESC3_CIC_INDEX		16