Commit 6adb8f38 authored Jun 19, 2009 by Paul Walmsley Committed by paul Jun 19, 2009

OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize



The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider.  This does not appear
to be necessary.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

parent cd07ecc8

arch/arm/mach-omap2/sram34xx.S

+0 −3

Original line number	Diff line number	Diff line
		@@ -102,9 +102,6 @@ configure_core_dpll:
		orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
		str r12, [r11]
		ldr r12, [r11] @ posted-write barrier for CM
		mov r12, #0x800 @ wait for the clock to stabilise
		cmp r3, #2
		bne wait_clk_stable
		bx lr
		wait_clk_stable:
		subs r12, r12, #1