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Commit 6aad8bf9 authored by Ray Jui's avatar Ray Jui Committed by Olof Johansson
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arm64: dts: Add Broadcom North Star 2 support 



Add Broadcom NS2 device tree binding document. Also add initial device
tree dtsi for Broadcom North Star 2 (NS2) SoC and board support for NS2
SVK board

Signed-off-by: default avatarJon Mason <jonmason@broadcom.com>
Signed-off-by: default avatarRay Jui <rjui@broadcom.com>
Reviewed-by: default avatarScott Branden <sbranden@broadcom.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 36b7c583

Documentation/devicetree/bindings/arm/bcm/ns2.txt

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Broadcom North Star 2 (NS2) device tree bindings

------------------------------------------------



Boards with NS2 shall have the following properties:



Required root node property:



NS2 SVK board

compatible = "brcm,ns2-svk", "brcm,ns2";

arch/arm64/boot/dts/Makefile

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dts-dirs += amd

dts-dirs += apm

dts-dirs += arm

dts-dirs += broadcom

dts-dirs += cavium

dts-dirs += exynos

dts-dirs += freescale

arch/arm64/boot/dts/broadcom/Makefile

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dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb



always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb

arch/arm64/boot/dts/broadcom/ns2-svk.dts

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/*

 *  BSD LICENSE

 *

 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.

 *

 *  Redistribution and use in source and binary forms, with or without

 *  modification, are permitted provided that the following conditions

 *  are met:

 *

 *    * Redistributions of source code must retain the above copyright

 *      notice, this list of conditions and the following disclaimer.

 *    * Redistributions in binary form must reproduce the above copyright

 *      notice, this list of conditions and the following disclaimer in

 *      the documentation and/or other materials provided with the

 *      distribution.

 *    * Neither the name of Broadcom Corporation nor the names of its

 *      contributors may be used to endorse or promote products derived

 *      from this software without specific prior written permission.

 *

 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/dts-v1/;



#include "ns2.dtsi"



/ {

	model = "Broadcom NS2 SVK";

	compatible = "brcm,ns2-svk", "brcm,ns2";



	aliases {

		serial0 = &uart3;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory {

		device_type = "memory";

		reg = <0x000000000 0x80000000 0x00000000 0x40000000>;

	};



	soc: soc {

		uart3: serial@66130000 {

			status = "ok";

		};

	};

};

arch/arm64/boot/dts/broadcom/ns2.dtsi

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/*

 *  BSD LICENSE

 *

 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.

 *

 *  Redistribution and use in source and binary forms, with or without

 *  modification, are permitted provided that the following conditions

 *  are met:

 *

 *    * Redistributions of source code must retain the above copyright

 *      notice, this list of conditions and the following disclaimer.

 *    * Redistributions in binary form must reproduce the above copyright

 *      notice, this list of conditions and the following disclaimer in

 *      the documentation and/or other materials provided with the

 *      distribution.

 *    * Neither the name of Broadcom Corporation nor the names of its

 *      contributors may be used to endorse or promote products derived

 *      from this software without specific prior written permission.

 *

 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/memreserve/ 0x84b00000 0x00000008;



/ {

	compatible = "brcm,ns2";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 0>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 1>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 2>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 3>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;



		gic: interrupt-controller@65210000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x65210000 0x1000>,

			      <0x65220000 0x1000>,

			      <0x65240000 0x2000>,

			      <0x65260000 0x1000>;

		};



		uart3: serial@66130000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x66130000 0x100>;

			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clock-frequency = <23961600>;

			status = "disabled";

		};

	};

};