Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6a588703 authored by James Liao's avatar James Liao Committed by Stephen Boyd
Browse files

dt-bindings: ARM: Mediatek: Document bindings for MT2701



This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.

Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: default avatarErin Lo <erin.lo@mediatek.com>
Tested-by: default avatarJohn Crispin <blogic@openwrt.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2886c846
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the system.

Required Properties:

- compatible: Should be:
- compatible: Should be one of:
	- "mediatek,mt2701-apmixedsys"
	- "mediatek,mt8135-apmixedsys"
	- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1
+22 −0
Original line number Diff line number Diff line
Mediatek bdpsys controller
============================

The Mediatek bdpsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1

The bdpsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

bdpsys: clock-controller@1c000000 {
	compatible = "mediatek,mt2701-bdpsys", "syscon";
	reg = <0 0x1c000000 0 0x1000>;
	#clock-cells = <1>;
};
+22 −0
Original line number Diff line number Diff line
Mediatek ethsys controller
============================

The Mediatek ethsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1

The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ethsys: clock-controller@1b000000 {
	compatible = "mediatek,mt2701-ethsys", "syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
};
+24 −0
Original line number Diff line number Diff line
Mediatek hifsys controller
============================

The Mediatek hifsys controller provides various clocks and reset
outputs to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1

The hifsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

hifsys: clock-controller@1a000000 {
	compatible = "mediatek,mt2701-hifsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};
+2 −1
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ The Mediatek imgsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
- compatible: Should be one of:
	- "mediatek,mt2701-imgsys", "syscon"
	- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1

Loading