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Commit 6a5278d0 authored by Prashant Gaikwad's avatar Prashant Gaikwad Committed by Stephen Warren
Browse files

ARM: tegra: add clk_prepare/clk_unprepare 



Use clk_prepare/clk_unprepare as required by the generic clk framework.

Tested on Ventana and Cardhu.

Signed-off-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent cfaf0251

arch/arm/mach-tegra/cpu-tegra.c

+3 −3
Original line number Diff line number Diff line
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) 
		return PTR_ERR(emc_clk);

	}



	clk_enable(emc_clk);

	clk_enable(cpu_clk);

	clk_prepare_enable(emc_clk);

	clk_prepare_enable(cpu_clk);



	cpufreq_frequency_table_cpuinfo(policy, freq_table);

	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) 
static int tegra_cpu_exit(struct cpufreq_policy *policy)

{

	cpufreq_frequency_table_cpuinfo(policy, freq_table);

	clk_disable(emc_clk);

	clk_disable_unprepare(emc_clk);

	clk_put(emc_clk);

	clk_put(cpu_clk);

	return 0;

arch/arm/mach-tegra/dma.c

+1 −1
Original line number Diff line number Diff line
@@ -720,7 +720,7 @@ int __init tegra_dma_init(void) 
		ret = PTR_ERR(c);

		goto fail;

	}

	ret = clk_enable(c);

	ret = clk_prepare_enable(c);

	if (ret != 0) {

		pr_err("Unable to enable clock for APB DMA\n");

		goto fail;

arch/arm/mach-tegra/pcie.c

+3 −3
Original line number Diff line number Diff line
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void) 


	tegra_pcie_xclk_clamp(false);



	clk_enable(tegra_pcie.afi_clk);

	clk_enable(tegra_pcie.pex_clk);

	return clk_enable(tegra_pcie.pll_e);

	clk_prepare_enable(tegra_pcie.afi_clk);

	clk_prepare_enable(tegra_pcie.pex_clk);

	return clk_prepare_enable(tegra_pcie.pll_e);

}



static int tegra_pcie_clocks_get(void)

arch/arm/mach-tegra/powergate.c

+2 −2
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) 
	if (ret)

		goto err_power;



	ret = clk_enable(clk);

	ret = clk_prepare_enable(clk);

	if (ret)

		goto err_clk;
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) 
	return 0;



err_clamp:

	clk_disable(clk);

	clk_disable_unprepare(clk);

err_clk:

	tegra_powergate_power_off(id);

err_power:

arch/arm/mach-tegra/timer.c

+2 −2
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ static void __init tegra_init_timer(void) 
			" Assuming 12Mhz input clock.\n");

		rate = 12000000;

	} else {

		clk_enable(clk);

		clk_prepare_enable(clk);

		rate = clk_get_rate(clk);

	}
@@ -201,7 +201,7 @@ static void __init tegra_init_timer(void) 
	if (IS_ERR(clk))

		pr_warn("Unable to get rtc-tegra clock\n");

	else

		clk_enable(clk);

		clk_prepare_enable(clk);



	switch (rate) {

	case 12000000: