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Commit 67acd8d5 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: clear execution hazard after changing FTLB enable 



On current P-series cores from Imagination the FTLB can be enabled or
disabled via a bit in the Config6 register, and an execution hazard is
created by changing the value of bit. The ftlb_disable function already
cleared that hazard but that does no good for other callers. Clear the
hazard in the set_ftlb_enable function that creates it, and only for the
cores where it applies.

This has the effect of reverting c982c6d6 ("MIPS: cpu-probe: Remove
cp0 hazard barrier when enabling the FTLB") which was incorrect.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Fixes: c982c6d6 ("MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14023/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ebd0e0f5

arch/mips/kernel/cpu-probe.c

+1 −2
Original line number Diff line number Diff line
@@ -376,8 +376,6 @@ static int __init ftlb_disable(char *s) 
		return 1;

	}



	back_to_back_c0_hazard();



	config4 = read_c0_config4();



	/* Check that FTLB has been disabled */
@@ -560,6 +558,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 
		}



		write_c0_config6(config);

		back_to_back_c0_hazard();

		break;

	case CPU_I6400:

		/* There's no way to disable the FTLB */