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Commit 6727f086 authored by Martin Sperl's avatar Martin Sperl Committed by Eric Anholt
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clk: bcm2835: pll_off should only update CM_PLL_ANARST 



bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b88 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: default avatarMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
parent 4d3ac666

drivers/clk/bcm/clk-bcm2835.c

+8 −2
Original line number Diff line number Diff line
@@ -910,8 +910,14 @@ static void bcm2835_pll_off(struct clk_hw *hw) 
	struct bcm2835_cprman *cprman = pll->cprman;

	const struct bcm2835_pll_data *data = pll->data;



	cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);

	cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);

	spin_lock(&cprman->regs_lock);

	cprman_write(cprman, data->cm_ctrl_reg,

		     cprman_read(cprman, data->cm_ctrl_reg) |

		     CM_PLL_ANARST);

	cprman_write(cprman, data->a2w_ctrl_reg,

		     cprman_read(cprman, data->a2w_ctrl_reg) |

		     A2W_PLL_CTRL_PWRDN);

	spin_unlock(&cprman->regs_lock);

}



static int bcm2835_pll_on(struct clk_hw *hw)