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Commit 66f6ff09 authored by Eric Anholt's avatar Eric Anholt
Browse files

agp/intel: Don't do the chipset flush on Sandybridge. 



This CPU should be coherent with graphics in this direction, though
flushing graphics caches are still required.  Fixes a system reset on
module load on Sandybridge with 4G+ memory.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 285aca8e

drivers/char/agp/intel-agp.c

+7 −2
Original line number Diff line number Diff line
@@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled); 
#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)



#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)



#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
@@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled); 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

		IS_SNB)



extern int agp_memory_reserved;
@@ -1204,6 +1206,9 @@ static void intel_i9xx_setup_flush(void) 
	if (intel_private.ifp_resource.start)

		return;



	if (IS_SNB)

		return;



	/* setup a resource for this object */

	intel_private.ifp_resource.name = "Intel Flush Page";

	intel_private.ifp_resource.flags = IORESOURCE_MEM;