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Commit 66ade474 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM fixes from Russell King:
 "Another round of ARM fixes, which include:
   - Fixing a problem with LPAE mapping sections
   - Reporting of some hwcaps on Krait CPUs
   - Avoiding repetitive warnings in the breakpoint code
   - Fixing a build error noticed on Dove platforms with PJ4 CPUs
   - Fix masking of level 2 cache revision.
   - Fixing timer-based udelay()
   - A larger fix for an erratum causing people major grief with Cortex
     A15 CPUs"

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7690/1: mm: fix CONFIG_LPAE typos
  ARM: 7689/1: add unwind annotations to ftrace asm
  ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops
  ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
  ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init
  ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs
  ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()
  ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs
  ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
  ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
  ARM: 7677/1: LPAE: Fix mapping in alloc_init_section for unaligned addresses
  ARM: KVM: vgic: take distributor lock on sync_hwstate path
  ARM: KVM: vgic: force EOIed LRs to the empty state
parents cbfa0e72 4e1db26a

arch/arm/Kconfig

+12 −2
Original line number Diff line number Diff line
@@ -1183,9 +1183,9 @@ config ARM_NR_BANKS 
	default 8



config IWMMXT

	bool "Enable iWMMXt support"

	bool "Enable iWMMXt support" if !CPU_PJ4

	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4

	default y if PXA27x || PXA3xx || ARCH_MMP

	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4

	help

	  Enable support for iWMMXt context switching at run time if

	  running on a CPU that supports it.
@@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420 
	 to deadlock. This workaround puts DSB before executing ISB if

	 an abort may occur on cache maintenance.



config ARM_ERRATA_798181

	bool "ARM errata: TLBI/DSB failure on Cortex-A15"

	depends on CPU_V7 && SMP

	help

	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not

	  adequately shooting down all use of the old entries. This

	  option enables the Linux kernel workaround for this erratum

	  which sends an IPI to the CPUs that are running the same ASID

	  as the one being invalidated.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/include/asm/delay.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ extern struct arm_delay_ops { 
	void (*delay)(unsigned long);

	void (*const_udelay)(unsigned long);

	void (*udelay)(unsigned long);

	bool const_clock;

	unsigned long ticks_per_jiffy;

} arm_delay_ops;



#define __delay(n)		arm_delay_ops.delay(n)

arch/arm/include/asm/highmem.h

+7 −0
Original line number Diff line number Diff line
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page); 
#endif

#endif



/*

 * Needed to be able to broadcast the TLB invalidation for kmap.

 */

#ifdef CONFIG_ARM_ERRATA_798181

#undef ARCH_NEEDS_KMAP_HIGH_GET

#endif



#ifdef ARCH_NEEDS_KMAP_HIGH_GET

extern void *kmap_high_get(struct page *page);

#else

arch/arm/include/asm/mmu_context.h

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); 
void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);

#define init_new_context(tsk,mm)	({ atomic64_set(&mm->context.id, 0); 0; })



DECLARE_PER_CPU(atomic64_t, active_asids);



#else	/* !CONFIG_CPU_HAS_ASID */



#ifdef CONFIG_MMU

arch/arm/include/asm/tlbflush.h

+15 −0
Original line number Diff line number Diff line
@@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void) 
		isb();

}



#ifdef CONFIG_ARM_ERRATA_798181

static inline void dummy_flush_tlb_a15_erratum(void)

{

	/*

	 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.

	 */

	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));

	dsb();

}

#else

static inline void dummy_flush_tlb_a15_erratum(void)

{

}

#endif



/*

 *	flush_pmd_entry

 *