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Commit 66a4a1fb authored by Thomas Abraham's avatar Thomas Abraham Committed by Krzysztof Kozlowski
Browse files

ARM: dts: Add CPU OPP properties for exynos542x/5800 



For Exynos542x/5800 platforms, add CPU operating points
for migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.

Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- merged Exynos5422 fixes from Ben

Changes by Ben Gamari:
- Port to operating-points-v2

Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: default avatarBen Gamari <ben@smart-cactus.org>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
parent 8b51c5e7

arch/arm/boot/dts/exynos5420-cpus.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -29,8 +29,10 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x0>;

			clocks = <&clock CLK_ARM_CLK>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu1: cpu@1 {
@@ -39,6 +41,7 @@ 
			reg = <0x1>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu2: cpu@2 {
@@ -47,6 +50,7 @@ 
			reg = <0x2>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu3: cpu@3 {
@@ -55,14 +59,17 @@ 
			reg = <0x3>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x100>;

			clocks = <&clock CLK_KFC_CLK>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu5: cpu@101 {
@@ -71,6 +78,7 @@ 
			reg = <0x101>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu6: cpu@102 {
@@ -79,6 +87,7 @@ 
			reg = <0x102>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu7: cpu@103 {
@@ -87,6 +96,7 @@ 
			reg = <0x103>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};

	};

};

arch/arm/boot/dts/exynos5420.dtsi

+110 −0
Original line number Diff line number Diff line
@@ -50,6 +50,116 @@ 
		usbdrdphy1 = &usbdrd_phy1;

	};



	cluster_a15_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;

		opp@1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <1250000>;

			clock-latency-ns = <140000>;

		};

		opp@1700000000 {

			opp-hz = /bits/ 64 <1700000000>;

			opp-microvolt = <1212500>;

			clock-latency-ns = <140000>;

		};

		opp@1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <1175000>;

			clock-latency-ns = <140000>;

		};

		opp@1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <1137500>;

			clock-latency-ns = <140000>;

		};

		opp@1400000000 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-microvolt = <1112500>;

			clock-latency-ns = <140000>;

		};

		opp@1300000000 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1062500>;

			clock-latency-ns = <140000>;

		};

		opp@1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1037500>;

			clock-latency-ns = <140000>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			opp-microvolt = <1012500>;

			clock-latency-ns = <140000>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = < 987500>;

			clock-latency-ns = <140000>;

		};

		opp@900000000 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = < 962500>;

			clock-latency-ns = <140000>;

		};

		opp@800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = < 937500>;

			clock-latency-ns = <140000>;

		};

		opp@700000000 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = < 912500>;

			clock-latency-ns = <140000>;

		};

	};



	cluster_a7_opp_table: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;

		opp@1300000000 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1275000>;

			clock-latency-ns = <140000>;

		};

		opp@1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1212500>;

			clock-latency-ns = <140000>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			opp-microvolt = <1162500>;

			clock-latency-ns = <140000>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <1112500>;

			clock-latency-ns = <140000>;

		};

		opp@900000000 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = <1062500>;

			clock-latency-ns = <140000>;

		};

		opp@800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <1025000>;

			clock-latency-ns = <140000>;

		};

		opp@700000000 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = <975000>;

			clock-latency-ns = <140000>;

		};

		opp@600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <937500>;

			clock-latency-ns = <140000>;

		};

	};



	/*

	 * The 'cpus' node is not present here but instead it is provided

	 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.

arch/arm/boot/dts/exynos5422-cpus.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -28,8 +28,10 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x100>;

			clocks = <&clock CLK_KFC_CLK>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu1: cpu@101 {
@@ -38,6 +40,7 @@ 
			reg = <0x101>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu2: cpu@102 {
@@ -46,6 +49,7 @@ 
			reg = <0x102>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu3: cpu@103 {
@@ -54,14 +58,17 @@ 
			reg = <0x103>;

			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

		};



		cpu4: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			clocks = <&clock CLK_ARM_CLK>;

			reg = <0x0>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu5: cpu@1 {
@@ -70,6 +77,7 @@ 
			reg = <0x1>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu6: cpu@2 {
@@ -78,6 +86,7 @@ 
			reg = <0x2>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};



		cpu7: cpu@3 {
@@ -86,6 +95,7 @@ 
			reg = <0x3>;

			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

		};

	};

};