Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 66188fb1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "Another round of fixes:

   - CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems
   - CPS: Avoid BUG() when offlining pre-r6 CPUs
   - DEC: Avoid gas warnings due to suspicious instruction scheduling by
     manually expanding assembler macros.
   - FTLB: Fix configuration by moving confiuguratoin after probing
   - FTLB: clear execution hazard after changing FTLB enable
   - Highmem: Fix detection of unsupported highmem with cache aliases
   - I6400: Don't touch FTLBP chicken bits
   - microMIPS: Fix BUILD_ROLLBACK_PROLOGUE
   - Malta: Fix IOCU disable switch read for MIPS64
   - Octeon: Fix probing of devices attached to GPIO lines
   - uprobes: Misc small fixes"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems
  MIPS: Fix detection of unsupported highmem with cache aliases
  MIPS: Malta: Fix IOCU disable switch read for MIPS64
  MIPS: Fix BUILD_ROLLBACK_PROLOGUE for microMIPS
  MIPS: clear execution hazard after changing FTLB enable
  MIPS: Configure FTLB after probing TLB sizes from config4
  MIPS: Stop setting I6400 FTLBP
  MIPS: DEC: Avoid la pseudo-instruction in delay slots
  MIPS: Octeon: mark GPIO controller node not populated after IRQ init.
  MIPS: uprobes: fix use of uninitialised variable
  MIPS: uprobes: remove incorrect set_orig_insn
  MIPS: fix uretprobe implementation
  MIPS: smp-cps: Avoid BUG() when offlining pre-r6 CPUs
parents 0c7fc30f 6605d156

arch/mips/cavium-octeon/octeon-irq.c

+6 −0
Original line number Diff line number Diff line
@@ -1619,6 +1619,12 @@ static int __init octeon_irq_init_gpio( 
		return -ENOMEM;

	}



	/*

	 * Clear the OF_POPULATED flag that was set by of_irq_init()

	 * so that all GPIO devices will be probed.

	 */

	of_node_clear_flag(gpio_node, OF_POPULATED);



	return 0;

}

/*

arch/mips/dec/int-handler.S

+38 −2
Original line number Diff line number Diff line
@@ -146,7 +146,25 @@ 
		/*

		 * Find irq with highest priority

		 */

		 PTR_LA	t1,cpu_mask_nr_tbl

		# open coded PTR_LA t1, cpu_mask_nr_tbl

#if (_MIPS_SZPTR == 32)

		# open coded la t1, cpu_mask_nr_tbl

		lui	t1, %hi(cpu_mask_nr_tbl)

		addiu	t1, %lo(cpu_mask_nr_tbl)



#endif

#if (_MIPS_SZPTR == 64)

		# open coded dla t1, cpu_mask_nr_tbl

		.set	push

		.set	noat

		lui	t1, %highest(cpu_mask_nr_tbl)

		lui	AT, %hi(cpu_mask_nr_tbl)

		daddiu	t1, t1, %higher(cpu_mask_nr_tbl)

		daddiu	AT, AT, %lo(cpu_mask_nr_tbl)

		dsll	t1, 32

		daddu	t1, t1, AT

		.set	pop

#endif

1:		lw	t2,(t1)

		nop

		and	t2,t0
@@ -195,7 +213,25 @@ 
		/*

		 * Find irq with highest priority

		 */

		 PTR_LA	t1,asic_mask_nr_tbl

		# open coded PTR_LA t1,asic_mask_nr_tbl

#if (_MIPS_SZPTR == 32)

		# open coded la t1, asic_mask_nr_tbl

		lui	t1, %hi(asic_mask_nr_tbl)

		addiu	t1, %lo(asic_mask_nr_tbl)



#endif

#if (_MIPS_SZPTR == 64)

		# open coded dla t1, asic_mask_nr_tbl

		.set	push

		.set	noat

		lui	t1, %highest(asic_mask_nr_tbl)

		lui	AT, %hi(asic_mask_nr_tbl)

		daddiu	t1, t1, %higher(asic_mask_nr_tbl)

		daddiu	AT, AT, %lo(asic_mask_nr_tbl)

		dsll	t1, 32

		daddu	t1, t1, AT

		.set	pop

#endif

2:		lw	t2,(t1)

		nop

		and	t2,t0

arch/mips/include/asm/mips-cm.h

+11 −0
Original line number Diff line number Diff line
@@ -458,10 +458,21 @@ static inline int mips_cm_revision(void) 
static inline unsigned int mips_cm_max_vp_width(void)

{

	extern int smp_num_siblings;

	uint32_t cfg;



	if (mips_cm_revision() >= CM_REV_CM3)

		return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;



	if (mips_cm_present()) {

		/*

		 * We presume that all cores in the system will have the same

		 * number of VP(E)s, and if that ever changes then this will

		 * need revisiting.

		 */

		cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;

		return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;

	}



	if (IS_ENABLED(CONFIG_SMP))

		return smp_num_siblings;

arch/mips/include/asm/mipsregs.h

+0 −2
Original line number Diff line number Diff line
@@ -660,8 +660,6 @@ 


#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)

#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)

/* FTLB probability bits for R6 */

#define MIPS_CONF7_FTLBP_SHIFT	(18)



/* WatchLo* register definitions */

#define MIPS_WATCHLO_IRW	(_ULCAST_(0x7) << 0)

arch/mips/include/asm/uprobes.h

+0 −1
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ struct arch_uprobe { 
	unsigned long	resume_epc;

	u32	insn[2];

	u32	ixol[2];

	union	mips_instruction orig_inst[MAX_UINSN_BYTES / 4];

};



struct arch_uprobe_task {