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Commit 65aaae24 authored by Pratyush Anand's avatar Pratyush Anand Committed by Bjorn Helgaas
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PCI: spear: Pass config resource through reg property



PCIe configuration space should be passed through reg property, rather than
through ranges property.  This patch does the correction for SPEAr13XX
SOCs.

Signed-off-by: default avatarPratyush Anand <pratyush.anand@st.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarMohit Kumar <mohit.kumar@st.com>
parent 52addcf9
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+9 −9
Original line number Diff line number Diff line
@@ -85,7 +85,8 @@

		pcie0: pcie@b1000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1000000 0x4000>;
			reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 68 0x4>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -95,15 +96,15 @@
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
			ranges = <0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			status = "disabled";
		};

		pcie1: pcie@b1800000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1800000 0x4000>;
			reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 69 0x4>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0x0 0 &gic 0 69 0x4>;
@@ -113,15 +114,15 @@
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */
				0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
			ranges = <0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
			status = "disabled";
		};

		pcie2: pcie@b4000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb4000000 0x4000>;
			reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 70 0x4>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0x0 0 &gic 0 70 0x4>;
@@ -131,8 +132,7 @@
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */
				0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
			ranges = <0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			status = "disabled";
		};
+3 −3
Original line number Diff line number Diff line
@@ -50,7 +50,8 @@

		pcie0: pcie@b1000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1000000 0x4000>;
			reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 68 0x4>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -60,8 +61,7 @@
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
			ranges = <0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			status = "disabled";
		};
+1 −1
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)

	pp->dev = dev;

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pp->dbi_base)) {
		dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);