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Commit 65844bb0 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm_mips_20150327' of... 

Merge tag 'kvm_mips_20150327' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips into kvm-next

MIPS KVM Guest FPU & SIMD (MSA) Support

Add guest FPU and MIPS SIMD Architecture (MSA) support to MIPS KVM, by
enabling the host FPU/MSA while in guest mode. This adds two new KVM
capabilities, KVM_CAP_MIPS_FPU & KVM_CAP_MIPS_MSA, and supports the 3 FP
register modes (FR=0, FR=1, FRE=1), and 128-bit MSA vector registers,
with lazy FPU/MSA context save and restore.

Some required MIPS FP/MSA fixes are merged in from a branch in the MIPS
tree first.
parents b3a2a907 d952bd07

Documentation/virtual/kvm/api.txt

+54 −0
Original line number Diff line number Diff line
@@ -1967,15 +1967,25 @@ registers, find a list below: 
  MIPS  | KVM_REG_MIPS_CP0_STATUS       | 32

  MIPS  | KVM_REG_MIPS_CP0_CAUSE        | 32

  MIPS  | KVM_REG_MIPS_CP0_EPC          | 64

  MIPS  | KVM_REG_MIPS_CP0_PRID         | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG       | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG1      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG2      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG3      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG4      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG5      | 32

  MIPS  | KVM_REG_MIPS_CP0_CONFIG7      | 32

  MIPS  | KVM_REG_MIPS_CP0_ERROREPC     | 64

  MIPS  | KVM_REG_MIPS_COUNT_CTL        | 64

  MIPS  | KVM_REG_MIPS_COUNT_RESUME     | 64

  MIPS  | KVM_REG_MIPS_COUNT_HZ         | 64

  MIPS  | KVM_REG_MIPS_FPR_32(0..31)    | 32

  MIPS  | KVM_REG_MIPS_FPR_64(0..31)    | 64

  MIPS  | KVM_REG_MIPS_VEC_128(0..31)   | 128

  MIPS  | KVM_REG_MIPS_FCR_IR           | 32

  MIPS  | KVM_REG_MIPS_FCR_CSR          | 32

  MIPS  | KVM_REG_MIPS_MSA_IR           | 32

  MIPS  | KVM_REG_MIPS_MSA_CSR          | 32



ARM registers are mapped using the lower 32 bits.  The upper 16 of that

is the register group type, or coprocessor number:
@@ -2029,6 +2039,25 @@ patterns depending on whether they're 32-bit or 64-bit registers: 
MIPS KVM control registers (see above) have the following id bit patterns:

  0x7030 0000 0002 <reg:16>



MIPS FPU registers (see KVM_REG_MIPS_FPR_{32,64}() above) have the following

id bit patterns depending on the size of the register being accessed. They are

always accessed according to the current guest FPU mode (Status.FR and

Config5.FRE), i.e. as the guest would see them, and they become unpredictable

if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector

registers (see KVM_REG_MIPS_VEC_128() above) have similar patterns as they

overlap the FPU registers:

  0x7020 0000 0003 00 <0:3> <reg:5> (32-bit FPU registers)

  0x7030 0000 0003 00 <0:3> <reg:5> (64-bit FPU registers)

  0x7040 0000 0003 00 <0:3> <reg:5> (128-bit MSA vector registers)



MIPS FPU control registers (see KVM_REG_MIPS_FCR_{IR,CSR} above) have the

following id bit patterns:

  0x7020 0000 0003 01 <0:3> <reg:5>



MIPS MSA control registers (see KVM_REG_MIPS_MSA_{IR,CSR} above) have the

following id bit patterns:

  0x7020 0000 0003 02 <0:3> <reg:5>





4.69 KVM_GET_ONE_REG
@@ -3293,6 +3322,31 @@ Parameters: none 
This capability enables the in-kernel irqchip for s390. Please refer to

"4.24 KVM_CREATE_IRQCHIP" for details.



6.9 KVM_CAP_MIPS_FPU



Architectures: mips

Target: vcpu

Parameters: args[0] is reserved for future use (should be 0).



This capability allows the use of the host Floating Point Unit by the guest. It

allows the Config1.FP bit to be set to enable the FPU in the guest. Once this is

done the KVM_REG_MIPS_FPR_* and KVM_REG_MIPS_FCR_* registers can be accessed

(depending on the current guest FPU register mode), and the Status.FR,

Config5.FRE bits are accessible via the KVM API and also from the guest,

depending on them being supported by the FPU.



6.10 KVM_CAP_MIPS_MSA



Architectures: mips

Target: vcpu

Parameters: args[0] is reserved for future use (should be 0).



This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.

It allows the Config3.MSAP bit to be set to enable the use of MSA by the guest.

Once this is done the KVM_REG_MIPS_VEC_* and KVM_REG_MIPS_MSA_* registers can be

accessed, and the Config5.MSAEn bit is accessible via the KVM API and also from

the guest.



7. Capabilities that can be enabled on VMs

------------------------------------------

arch/mips/include/asm/asmmacro-32.h

+64 −64
Original line number Diff line number Diff line
@@ -16,38 +16,38 @@ 
	.set push

	SET_HARDFLOAT

	cfc1	\tmp,  fcr31

	swc1	$f0,  THREAD_FPR0_LS64(\thread)

	swc1	$f1,  THREAD_FPR1_LS64(\thread)

	swc1	$f2,  THREAD_FPR2_LS64(\thread)

	swc1	$f3,  THREAD_FPR3_LS64(\thread)

	swc1	$f4,  THREAD_FPR4_LS64(\thread)

	swc1	$f5,  THREAD_FPR5_LS64(\thread)

	swc1	$f6,  THREAD_FPR6_LS64(\thread)

	swc1	$f7,  THREAD_FPR7_LS64(\thread)

	swc1	$f8,  THREAD_FPR8_LS64(\thread)

	swc1	$f9,  THREAD_FPR9_LS64(\thread)

	swc1	$f10, THREAD_FPR10_LS64(\thread)

	swc1	$f11, THREAD_FPR11_LS64(\thread)

	swc1	$f12, THREAD_FPR12_LS64(\thread)

	swc1	$f13, THREAD_FPR13_LS64(\thread)

	swc1	$f14, THREAD_FPR14_LS64(\thread)

	swc1	$f15, THREAD_FPR15_LS64(\thread)

	swc1	$f16, THREAD_FPR16_LS64(\thread)

	swc1	$f17, THREAD_FPR17_LS64(\thread)

	swc1	$f18, THREAD_FPR18_LS64(\thread)

	swc1	$f19, THREAD_FPR19_LS64(\thread)

	swc1	$f20, THREAD_FPR20_LS64(\thread)

	swc1	$f21, THREAD_FPR21_LS64(\thread)

	swc1	$f22, THREAD_FPR22_LS64(\thread)

	swc1	$f23, THREAD_FPR23_LS64(\thread)

	swc1	$f24, THREAD_FPR24_LS64(\thread)

	swc1	$f25, THREAD_FPR25_LS64(\thread)

	swc1	$f26, THREAD_FPR26_LS64(\thread)

	swc1	$f27, THREAD_FPR27_LS64(\thread)

	swc1	$f28, THREAD_FPR28_LS64(\thread)

	swc1	$f29, THREAD_FPR29_LS64(\thread)

	swc1	$f30, THREAD_FPR30_LS64(\thread)

	swc1	$f31, THREAD_FPR31_LS64(\thread)

	swc1	$f0,  THREAD_FPR0(\thread)

	swc1	$f1,  THREAD_FPR1(\thread)

	swc1	$f2,  THREAD_FPR2(\thread)

	swc1	$f3,  THREAD_FPR3(\thread)

	swc1	$f4,  THREAD_FPR4(\thread)

	swc1	$f5,  THREAD_FPR5(\thread)

	swc1	$f6,  THREAD_FPR6(\thread)

	swc1	$f7,  THREAD_FPR7(\thread)

	swc1	$f8,  THREAD_FPR8(\thread)

	swc1	$f9,  THREAD_FPR9(\thread)

	swc1	$f10, THREAD_FPR10(\thread)

	swc1	$f11, THREAD_FPR11(\thread)

	swc1	$f12, THREAD_FPR12(\thread)

	swc1	$f13, THREAD_FPR13(\thread)

	swc1	$f14, THREAD_FPR14(\thread)

	swc1	$f15, THREAD_FPR15(\thread)

	swc1	$f16, THREAD_FPR16(\thread)

	swc1	$f17, THREAD_FPR17(\thread)

	swc1	$f18, THREAD_FPR18(\thread)

	swc1	$f19, THREAD_FPR19(\thread)

	swc1	$f20, THREAD_FPR20(\thread)

	swc1	$f21, THREAD_FPR21(\thread)

	swc1	$f22, THREAD_FPR22(\thread)

	swc1	$f23, THREAD_FPR23(\thread)

	swc1	$f24, THREAD_FPR24(\thread)

	swc1	$f25, THREAD_FPR25(\thread)

	swc1	$f26, THREAD_FPR26(\thread)

	swc1	$f27, THREAD_FPR27(\thread)

	swc1	$f28, THREAD_FPR28(\thread)

	swc1	$f29, THREAD_FPR29(\thread)

	swc1	$f30, THREAD_FPR30(\thread)

	swc1	$f31, THREAD_FPR31(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set pop

	.endm
@@ -56,38 +56,38 @@ 
	.set push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	lwc1	$f0,  THREAD_FPR0_LS64(\thread)

	lwc1	$f1,  THREAD_FPR1_LS64(\thread)

	lwc1	$f2,  THREAD_FPR2_LS64(\thread)

	lwc1	$f3,  THREAD_FPR3_LS64(\thread)

	lwc1	$f4,  THREAD_FPR4_LS64(\thread)

	lwc1	$f5,  THREAD_FPR5_LS64(\thread)

	lwc1	$f6,  THREAD_FPR6_LS64(\thread)

	lwc1	$f7,  THREAD_FPR7_LS64(\thread)

	lwc1	$f8,  THREAD_FPR8_LS64(\thread)

	lwc1	$f9,  THREAD_FPR9_LS64(\thread)

	lwc1	$f10, THREAD_FPR10_LS64(\thread)

	lwc1	$f11, THREAD_FPR11_LS64(\thread)

	lwc1	$f12, THREAD_FPR12_LS64(\thread)

	lwc1	$f13, THREAD_FPR13_LS64(\thread)

	lwc1	$f14, THREAD_FPR14_LS64(\thread)

	lwc1	$f15, THREAD_FPR15_LS64(\thread)

	lwc1	$f16, THREAD_FPR16_LS64(\thread)

	lwc1	$f17, THREAD_FPR17_LS64(\thread)

	lwc1	$f18, THREAD_FPR18_LS64(\thread)

	lwc1	$f19, THREAD_FPR19_LS64(\thread)

	lwc1	$f20, THREAD_FPR20_LS64(\thread)

	lwc1	$f21, THREAD_FPR21_LS64(\thread)

	lwc1	$f22, THREAD_FPR22_LS64(\thread)

	lwc1	$f23, THREAD_FPR23_LS64(\thread)

	lwc1	$f24, THREAD_FPR24_LS64(\thread)

	lwc1	$f25, THREAD_FPR25_LS64(\thread)

	lwc1	$f26, THREAD_FPR26_LS64(\thread)

	lwc1	$f27, THREAD_FPR27_LS64(\thread)

	lwc1	$f28, THREAD_FPR28_LS64(\thread)

	lwc1	$f29, THREAD_FPR29_LS64(\thread)

	lwc1	$f30, THREAD_FPR30_LS64(\thread)

	lwc1	$f31, THREAD_FPR31_LS64(\thread)

	lwc1	$f0,  THREAD_FPR0(\thread)

	lwc1	$f1,  THREAD_FPR1(\thread)

	lwc1	$f2,  THREAD_FPR2(\thread)

	lwc1	$f3,  THREAD_FPR3(\thread)

	lwc1	$f4,  THREAD_FPR4(\thread)

	lwc1	$f5,  THREAD_FPR5(\thread)

	lwc1	$f6,  THREAD_FPR6(\thread)

	lwc1	$f7,  THREAD_FPR7(\thread)

	lwc1	$f8,  THREAD_FPR8(\thread)

	lwc1	$f9,  THREAD_FPR9(\thread)

	lwc1	$f10, THREAD_FPR10(\thread)

	lwc1	$f11, THREAD_FPR11(\thread)

	lwc1	$f12, THREAD_FPR12(\thread)

	lwc1	$f13, THREAD_FPR13(\thread)

	lwc1	$f14, THREAD_FPR14(\thread)

	lwc1	$f15, THREAD_FPR15(\thread)

	lwc1	$f16, THREAD_FPR16(\thread)

	lwc1	$f17, THREAD_FPR17(\thread)

	lwc1	$f18, THREAD_FPR18(\thread)

	lwc1	$f19, THREAD_FPR19(\thread)

	lwc1	$f20, THREAD_FPR20(\thread)

	lwc1	$f21, THREAD_FPR21(\thread)

	lwc1	$f22, THREAD_FPR22(\thread)

	lwc1	$f23, THREAD_FPR23(\thread)

	lwc1	$f24, THREAD_FPR24(\thread)

	lwc1	$f25, THREAD_FPR25(\thread)

	lwc1	$f26, THREAD_FPR26(\thread)

	lwc1	$f27, THREAD_FPR27(\thread)

	lwc1	$f28, THREAD_FPR28(\thread)

	lwc1	$f29, THREAD_FPR29(\thread)

	lwc1	$f30, THREAD_FPR30(\thread)

	lwc1	$f31, THREAD_FPR31(\thread)

	ctc1	\tmp, fcr31

	.set pop

	.endm

arch/mips/include/asm/asmmacro.h

+127 −91
Original line number Diff line number Diff line
@@ -60,22 +60,22 @@ 
	.set	push

	SET_HARDFLOAT

	cfc1	\tmp, fcr31

	sdc1	$f0,  THREAD_FPR0_LS64(\thread)

	sdc1	$f2,  THREAD_FPR2_LS64(\thread)

	sdc1	$f4,  THREAD_FPR4_LS64(\thread)

	sdc1	$f6,  THREAD_FPR6_LS64(\thread)

	sdc1	$f8,  THREAD_FPR8_LS64(\thread)

	sdc1	$f10, THREAD_FPR10_LS64(\thread)

	sdc1	$f12, THREAD_FPR12_LS64(\thread)

	sdc1	$f14, THREAD_FPR14_LS64(\thread)

	sdc1	$f16, THREAD_FPR16_LS64(\thread)

	sdc1	$f18, THREAD_FPR18_LS64(\thread)

	sdc1	$f20, THREAD_FPR20_LS64(\thread)

	sdc1	$f22, THREAD_FPR22_LS64(\thread)

	sdc1	$f24, THREAD_FPR24_LS64(\thread)

	sdc1	$f26, THREAD_FPR26_LS64(\thread)

	sdc1	$f28, THREAD_FPR28_LS64(\thread)

	sdc1	$f30, THREAD_FPR30_LS64(\thread)

	sdc1	$f0,  THREAD_FPR0(\thread)

	sdc1	$f2,  THREAD_FPR2(\thread)

	sdc1	$f4,  THREAD_FPR4(\thread)

	sdc1	$f6,  THREAD_FPR6(\thread)

	sdc1	$f8,  THREAD_FPR8(\thread)

	sdc1	$f10, THREAD_FPR10(\thread)

	sdc1	$f12, THREAD_FPR12(\thread)

	sdc1	$f14, THREAD_FPR14(\thread)

	sdc1	$f16, THREAD_FPR16(\thread)

	sdc1	$f18, THREAD_FPR18(\thread)

	sdc1	$f20, THREAD_FPR20(\thread)

	sdc1	$f22, THREAD_FPR22(\thread)

	sdc1	$f24, THREAD_FPR24(\thread)

	sdc1	$f26, THREAD_FPR26(\thread)

	sdc1	$f28, THREAD_FPR28(\thread)

	sdc1	$f30, THREAD_FPR30(\thread)

	sw	\tmp, THREAD_FCR31(\thread)

	.set	pop

	.endm
@@ -84,22 +84,22 @@ 
	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	sdc1	$f1,  THREAD_FPR1_LS64(\thread)

	sdc1	$f3,  THREAD_FPR3_LS64(\thread)

	sdc1	$f5,  THREAD_FPR5_LS64(\thread)

	sdc1	$f7,  THREAD_FPR7_LS64(\thread)

	sdc1	$f9,  THREAD_FPR9_LS64(\thread)

	sdc1	$f11, THREAD_FPR11_LS64(\thread)

	sdc1	$f13, THREAD_FPR13_LS64(\thread)

	sdc1	$f15, THREAD_FPR15_LS64(\thread)

	sdc1	$f17, THREAD_FPR17_LS64(\thread)

	sdc1	$f19, THREAD_FPR19_LS64(\thread)

	sdc1	$f21, THREAD_FPR21_LS64(\thread)

	sdc1	$f23, THREAD_FPR23_LS64(\thread)

	sdc1	$f25, THREAD_FPR25_LS64(\thread)

	sdc1	$f27, THREAD_FPR27_LS64(\thread)

	sdc1	$f29, THREAD_FPR29_LS64(\thread)

	sdc1	$f31, THREAD_FPR31_LS64(\thread)

	sdc1	$f1,  THREAD_FPR1(\thread)

	sdc1	$f3,  THREAD_FPR3(\thread)

	sdc1	$f5,  THREAD_FPR5(\thread)

	sdc1	$f7,  THREAD_FPR7(\thread)

	sdc1	$f9,  THREAD_FPR9(\thread)

	sdc1	$f11, THREAD_FPR11(\thread)

	sdc1	$f13, THREAD_FPR13(\thread)

	sdc1	$f15, THREAD_FPR15(\thread)

	sdc1	$f17, THREAD_FPR17(\thread)

	sdc1	$f19, THREAD_FPR19(\thread)

	sdc1	$f21, THREAD_FPR21(\thread)

	sdc1	$f23, THREAD_FPR23(\thread)

	sdc1	$f25, THREAD_FPR25(\thread)

	sdc1	$f27, THREAD_FPR27(\thread)

	sdc1	$f29, THREAD_FPR29(\thread)

	sdc1	$f31, THREAD_FPR31(\thread)

	.set	pop

	.endm
@@ -118,22 +118,22 @@ 
	.set	push

	SET_HARDFLOAT

	lw	\tmp, THREAD_FCR31(\thread)

	ldc1	$f0,  THREAD_FPR0_LS64(\thread)

	ldc1	$f2,  THREAD_FPR2_LS64(\thread)

	ldc1	$f4,  THREAD_FPR4_LS64(\thread)

	ldc1	$f6,  THREAD_FPR6_LS64(\thread)

	ldc1	$f8,  THREAD_FPR8_LS64(\thread)

	ldc1	$f10, THREAD_FPR10_LS64(\thread)

	ldc1	$f12, THREAD_FPR12_LS64(\thread)

	ldc1	$f14, THREAD_FPR14_LS64(\thread)

	ldc1	$f16, THREAD_FPR16_LS64(\thread)

	ldc1	$f18, THREAD_FPR18_LS64(\thread)

	ldc1	$f20, THREAD_FPR20_LS64(\thread)

	ldc1	$f22, THREAD_FPR22_LS64(\thread)

	ldc1	$f24, THREAD_FPR24_LS64(\thread)

	ldc1	$f26, THREAD_FPR26_LS64(\thread)

	ldc1	$f28, THREAD_FPR28_LS64(\thread)

	ldc1	$f30, THREAD_FPR30_LS64(\thread)

	ldc1	$f0,  THREAD_FPR0(\thread)

	ldc1	$f2,  THREAD_FPR2(\thread)

	ldc1	$f4,  THREAD_FPR4(\thread)

	ldc1	$f6,  THREAD_FPR6(\thread)

	ldc1	$f8,  THREAD_FPR8(\thread)

	ldc1	$f10, THREAD_FPR10(\thread)

	ldc1	$f12, THREAD_FPR12(\thread)

	ldc1	$f14, THREAD_FPR14(\thread)

	ldc1	$f16, THREAD_FPR16(\thread)

	ldc1	$f18, THREAD_FPR18(\thread)

	ldc1	$f20, THREAD_FPR20(\thread)

	ldc1	$f22, THREAD_FPR22(\thread)

	ldc1	$f24, THREAD_FPR24(\thread)

	ldc1	$f26, THREAD_FPR26(\thread)

	ldc1	$f28, THREAD_FPR28(\thread)

	ldc1	$f30, THREAD_FPR30(\thread)

	ctc1	\tmp, fcr31

	.endm
@@ -141,22 +141,22 @@ 
	.set	push

	.set	mips64r2

	SET_HARDFLOAT

	ldc1	$f1,  THREAD_FPR1_LS64(\thread)

	ldc1	$f3,  THREAD_FPR3_LS64(\thread)

	ldc1	$f5,  THREAD_FPR5_LS64(\thread)

	ldc1	$f7,  THREAD_FPR7_LS64(\thread)

	ldc1	$f9,  THREAD_FPR9_LS64(\thread)

	ldc1	$f11, THREAD_FPR11_LS64(\thread)

	ldc1	$f13, THREAD_FPR13_LS64(\thread)

	ldc1	$f15, THREAD_FPR15_LS64(\thread)

	ldc1	$f17, THREAD_FPR17_LS64(\thread)

	ldc1	$f19, THREAD_FPR19_LS64(\thread)

	ldc1	$f21, THREAD_FPR21_LS64(\thread)

	ldc1	$f23, THREAD_FPR23_LS64(\thread)

	ldc1	$f25, THREAD_FPR25_LS64(\thread)

	ldc1	$f27, THREAD_FPR27_LS64(\thread)

	ldc1	$f29, THREAD_FPR29_LS64(\thread)

	ldc1	$f31, THREAD_FPR31_LS64(\thread)

	ldc1	$f1,  THREAD_FPR1(\thread)

	ldc1	$f3,  THREAD_FPR3(\thread)

	ldc1	$f5,  THREAD_FPR5(\thread)

	ldc1	$f7,  THREAD_FPR7(\thread)

	ldc1	$f9,  THREAD_FPR9(\thread)

	ldc1	$f11, THREAD_FPR11(\thread)

	ldc1	$f13, THREAD_FPR13(\thread)

	ldc1	$f15, THREAD_FPR15(\thread)

	ldc1	$f17, THREAD_FPR17(\thread)

	ldc1	$f19, THREAD_FPR19(\thread)

	ldc1	$f21, THREAD_FPR21(\thread)

	ldc1	$f23, THREAD_FPR23(\thread)

	ldc1	$f25, THREAD_FPR25(\thread)

	ldc1	$f27, THREAD_FPR27(\thread)

	ldc1	$f29, THREAD_FPR29(\thread)

	ldc1	$f31, THREAD_FPR31(\thread)

	.set	pop

	.endm
@@ -211,6 +211,22 @@ 
	.endm



#ifdef TOOLCHAIN_SUPPORTS_MSA

	.macro	_cfcmsa	rd, cs

	.set	push

	.set	mips32r2

	.set	msa

	cfcmsa	\rd, $\cs

	.set	pop

	.endm



	.macro	_ctcmsa	cd, rs

	.set	push

	.set	mips32r2

	.set	msa

	ctcmsa	$\cd, \rs

	.set	pop

	.endm



	.macro	ld_d	wd, off, base

	.set	push

	.set	mips32r2
@@ -227,35 +243,35 @@ 
	.set	pop

	.endm



	.macro	copy_u_w	rd, ws, n

	.macro	copy_u_w	ws, n

	.set	push

	.set	mips32r2

	.set	msa

	copy_u.w \rd, $w\ws[\n]

	copy_u.w $1, $w\ws[\n]

	.set	pop

	.endm



	.macro	copy_u_d	rd, ws, n

	.macro	copy_u_d	ws, n

	.set	push

	.set	mips64r2

	.set	msa

	copy_u.d \rd, $w\ws[\n]

	copy_u.d $1, $w\ws[\n]

	.set	pop

	.endm



	.macro	insert_w	wd, n, rs

	.macro	insert_w	wd, n

	.set	push

	.set	mips32r2

	.set	msa

	insert.w $w\wd[\n], \rs

	insert.w $w\wd[\n], $1

	.set	pop

	.endm



	.macro	insert_d	wd, n, rs

	.macro	insert_d	wd, n

	.set	push

	.set	mips64r2

	.set	msa

	insert.d $w\wd[\n], \rs

	insert.d $w\wd[\n], $1

	.set	pop

	.endm

#else
@@ -283,7 +299,7 @@ 
	/*

	 * Temporary until all toolchains in use include MSA support.

	 */

	.macro	cfcmsa	rd, cs

	.macro	_cfcmsa	rd, cs

	.set	push

	.set	noat

	SET_HARDFLOAT
@@ -293,7 +309,7 @@ 
	.set	pop

	.endm



	.macro	ctcmsa	cd, rs

	.macro	_ctcmsa	cd, rs

	.set	push

	.set	noat

	SET_HARDFLOAT
@@ -320,44 +336,36 @@ 
	.set	pop

	.endm



	.macro	copy_u_w	rd, ws, n

	.macro	copy_u_w	ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */

	or	\rd, $1, zero

	.set	pop

	.endm



	.macro	copy_u_d	rd, ws, n

	.macro	copy_u_d	ws, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	.insn

	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)

	/* move triggers an assembler bug... */

	or	\rd, $1, zero

	.set	pop

	.endm



	.macro	insert_w	wd, n, rs

	.macro	insert_w	wd, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)

	.set	pop

	.endm



	.macro	insert_d	wd, n, rs

	.macro	insert_d	wd, n

	.set	push

	.set	noat

	SET_HARDFLOAT

	/* move triggers an assembler bug... */

	or	$1, \rs, zero

	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)

	.set	pop

	.endm
@@ -399,7 +407,7 @@ 
	.set	push

	.set	noat

	SET_HARDFLOAT

	cfcmsa	$1, MSA_CSR

	_cfcmsa	$1, MSA_CSR

	sw	$1, THREAD_MSA_CSR(\thread)

	.set	pop

	.endm
@@ -409,7 +417,7 @@ 
	.set	noat

	SET_HARDFLOAT

	lw	$1, THREAD_MSA_CSR(\thread)

	ctcmsa	MSA_CSR, $1

	_ctcmsa	MSA_CSR, $1

	.set	pop

	ld_d	0, THREAD_FPR0, \thread

	ld_d	1, THREAD_FPR1, \thread
@@ -452,9 +460,6 @@ 
	insert_w \wd, 2

	insert_w \wd, 3

#endif

	.if	31-\wd

	msa_init_upper	(\wd+1)

	.endif

	.endm



	.macro	msa_init_all_upper
@@ -463,6 +468,37 @@ 
	SET_HARDFLOAT

	not	$1, zero

	msa_init_upper	0

	msa_init_upper	1

	msa_init_upper	2

	msa_init_upper	3

	msa_init_upper	4

	msa_init_upper	5

	msa_init_upper	6

	msa_init_upper	7

	msa_init_upper	8

	msa_init_upper	9

	msa_init_upper	10

	msa_init_upper	11

	msa_init_upper	12

	msa_init_upper	13

	msa_init_upper	14

	msa_init_upper	15

	msa_init_upper	16

	msa_init_upper	17

	msa_init_upper	18

	msa_init_upper	19

	msa_init_upper	20

	msa_init_upper	21

	msa_init_upper	22

	msa_init_upper	23

	msa_init_upper	24

	msa_init_upper	25

	msa_init_upper	26

	msa_init_upper	27

	msa_init_upper	28

	msa_init_upper	29

	msa_init_upper	30

	msa_init_upper	31

	.set	pop

	.endm

arch/mips/include/asm/fpu.h

+13 −7
Original line number Diff line number Diff line
@@ -48,6 +48,12 @@ enum fpu_mode { 
#define FPU_FR_MASK		0x1

};



#define __disable_fpu()							\

do {									\

	clear_c0_status(ST0_CU1);					\

	disable_fpu_hazard();						\

} while (0)



static inline int __enable_fpu(enum fpu_mode mode)

{

	int fr;
@@ -86,7 +92,12 @@ static inline int __enable_fpu(enum fpu_mode mode) 
		enable_fpu_hazard();



		/* check FR has the desired value */

		return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;

		if (!!(read_c0_status() & ST0_FR) == !!fr)

			return 0;



		/* unsupported FR value */

		__disable_fpu();

		return SIGFPE;



	default:

		BUG();
@@ -95,12 +106,6 @@ static inline int __enable_fpu(enum fpu_mode mode) 
	return SIGFPE;

}



#define __disable_fpu()							\

do {									\

	clear_c0_status(ST0_CU1);					\

	disable_fpu_hazard();						\

} while (0)



#define clear_fpu_owner()	clear_thread_flag(TIF_USEDFPU)



static inline int __is_fpu_owner(void)
@@ -170,6 +175,7 @@ static inline void lose_fpu(int save) 
		}

		disable_msa();

		clear_thread_flag(TIF_USEDMSA);

		__disable_fpu();

	} else if (is_fpu_owner()) {

		if (save)

			_save_fp(current);

arch/mips/include/asm/kdebug.h

+2 −1
Original line number Diff line number Diff line
@@ -10,7 +10,8 @@ enum die_val { 
	DIE_RI,

	DIE_PAGE_FAULT,

	DIE_BREAK,

	DIE_SSTEPBP

	DIE_SSTEPBP,

	DIE_MSAFP

};



#endif /* _ASM_MIPS_KDEBUG_H */