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Commit 652538c4 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth
Browse files

ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD 



Marvell Berlin BG2 has three, BG2CD just one pxav3 compatible
sdhci controllers, add them to the corresponding DT SoC
includes.

Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 60daa9f7

arch/arm/boot/dts/berlin2.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -53,6 +53,35 @@ 


		ranges = <0 0xf7000000 0x1000000>;



		sdhci0: sdhci@ab0000 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab0000 0x200>;

			clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;

			clock-names = "io", "core";

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		sdhci1: sdhci@ab0800 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab0800 0x200>;

			clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;

			clock-names = "io", "core";

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		sdhci2: sdhci@ab1000 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab1000 0x200>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;

			clock-names = "io", "core";

			pinctrl-0 = <&emmc_pmux>;

			pinctrl-names = "default";

			status = "disabled";

		};



		l2: l2-cache-controller@ac0000 {

			compatible = "marvell,tauros3-cache", "arm,pl310-cache";

			reg = <0xac0000 0x1000>;
@@ -289,6 +318,11 @@ 
			reg = <0xea0000 0x400>;

			clocks = <&refclk>;

			clock-names = "refclk";



			emmc_pmux: emmc-pmux {

				groups = "G26";

				function = "emmc";

			};

		};



		apb@fc0000 {

arch/arm/boot/dts/berlin2cd.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -45,6 +45,15 @@ 


		ranges = <0 0xf7000000 0x1000000>;



		sdhci0: sdhci@ab0000 {

			compatible = "mrvl,pxav3-mmc";

			reg = <0xab0000 0x200>;

			clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;

			clock-names = "io", "core";

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		l2: l2-cache-controller@ac0000 {

			compatible = "arm,pl310-cache";

			reg = <0xac0000 0x1000>;