Loading drivers/pci/hotplug/pciehp.h +0 −4 Original line number Diff line number Diff line Loading @@ -149,10 +149,6 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status); int pciehp_set_attention_status(struct slot *slot, u8 status); int pciehp_get_latch_status(struct slot *slot, u8 *status); int pciehp_get_adapter_status(struct slot *slot, u8 *status); int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed); int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val); int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed); int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val); int pciehp_query_power_fault(struct slot *slot); void pciehp_green_led_on(struct slot *slot); void pciehp_green_led_off(struct slot *slot); Loading drivers/pci/hotplug/pciehp_hpc.c +0 −101 Original line number Diff line number Diff line Loading @@ -705,107 +705,6 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) return IRQ_HANDLED; } int pciehp_get_max_lnk_width(struct slot *slot, enum pcie_link_width *value) { struct controller *ctrl = slot->ctrl; enum pcie_link_width lnk_wdth; u32 lnk_cap; int retval = 0; retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); if (retval) { ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); return retval; } switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ case 0: lnk_wdth = PCIE_LNK_WIDTH_RESRV; break; case 1: lnk_wdth = PCIE_LNK_X1; break; case 2: lnk_wdth = PCIE_LNK_X2; break; case 4: lnk_wdth = PCIE_LNK_X4; break; case 8: lnk_wdth = PCIE_LNK_X8; break; case 12: lnk_wdth = PCIE_LNK_X12; break; case 16: lnk_wdth = PCIE_LNK_X16; break; case 32: lnk_wdth = PCIE_LNK_X32; break; default: lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; break; } *value = lnk_wdth; ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); return retval; } int pciehp_get_cur_lnk_width(struct slot *slot, enum pcie_link_width *value) { struct controller *ctrl = slot->ctrl; enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; int retval = 0; u16 lnk_status; retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); if (retval) { ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", __func__); return retval; } switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ case 0: lnk_wdth = PCIE_LNK_WIDTH_RESRV; break; case 1: lnk_wdth = PCIE_LNK_X1; break; case 2: lnk_wdth = PCIE_LNK_X2; break; case 4: lnk_wdth = PCIE_LNK_X4; break; case 8: lnk_wdth = PCIE_LNK_X8; break; case 12: lnk_wdth = PCIE_LNK_X12; break; case 16: lnk_wdth = PCIE_LNK_X16; break; case 32: lnk_wdth = PCIE_LNK_X32; break; default: lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; break; } *value = lnk_wdth; ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); return retval; } int pcie_enable_notification(struct controller *ctrl) { u16 cmd, mask; Loading Loading
drivers/pci/hotplug/pciehp.h +0 −4 Original line number Diff line number Diff line Loading @@ -149,10 +149,6 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status); int pciehp_set_attention_status(struct slot *slot, u8 status); int pciehp_get_latch_status(struct slot *slot, u8 *status); int pciehp_get_adapter_status(struct slot *slot, u8 *status); int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed); int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val); int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed); int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val); int pciehp_query_power_fault(struct slot *slot); void pciehp_green_led_on(struct slot *slot); void pciehp_green_led_off(struct slot *slot); Loading
drivers/pci/hotplug/pciehp_hpc.c +0 −101 Original line number Diff line number Diff line Loading @@ -705,107 +705,6 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) return IRQ_HANDLED; } int pciehp_get_max_lnk_width(struct slot *slot, enum pcie_link_width *value) { struct controller *ctrl = slot->ctrl; enum pcie_link_width lnk_wdth; u32 lnk_cap; int retval = 0; retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); if (retval) { ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); return retval; } switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ case 0: lnk_wdth = PCIE_LNK_WIDTH_RESRV; break; case 1: lnk_wdth = PCIE_LNK_X1; break; case 2: lnk_wdth = PCIE_LNK_X2; break; case 4: lnk_wdth = PCIE_LNK_X4; break; case 8: lnk_wdth = PCIE_LNK_X8; break; case 12: lnk_wdth = PCIE_LNK_X12; break; case 16: lnk_wdth = PCIE_LNK_X16; break; case 32: lnk_wdth = PCIE_LNK_X32; break; default: lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; break; } *value = lnk_wdth; ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); return retval; } int pciehp_get_cur_lnk_width(struct slot *slot, enum pcie_link_width *value) { struct controller *ctrl = slot->ctrl; enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; int retval = 0; u16 lnk_status; retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); if (retval) { ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", __func__); return retval; } switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ case 0: lnk_wdth = PCIE_LNK_WIDTH_RESRV; break; case 1: lnk_wdth = PCIE_LNK_X1; break; case 2: lnk_wdth = PCIE_LNK_X2; break; case 4: lnk_wdth = PCIE_LNK_X4; break; case 8: lnk_wdth = PCIE_LNK_X8; break; case 12: lnk_wdth = PCIE_LNK_X12; break; case 16: lnk_wdth = PCIE_LNK_X16; break; case 32: lnk_wdth = PCIE_LNK_X32; break; default: lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; break; } *value = lnk_wdth; ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); return retval; } int pcie_enable_notification(struct controller *ctrl) { u16 cmd, mask; Loading