Merge branch 'omap4_upstream' of... (61f4a10c) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/mach-omap2/board-4430sdp.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
		};

		static struct omap_uart_config sdp4430_uart_config __initdata = {
		.enabled_uarts = (1 << 0) \| (1 << 1) \| (1 << 2),
		.enabled_uarts = (1 << 0) \| (1 << 1) \| (1 << 2) \| (1 << 3),
		};

		static struct omap_lcd_config sdp4430_lcd_config __initdata = {

arch/arm/mach-omap2/mcbsp.c

+41 −0

Original line number	Diff line number	Diff line
		@@ -169,6 +169,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
		#define OMAP34XX_MCBSP_PDATA_SZ 0
		#endif

		static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
		{
		.phys_base = OMAP44XX_MCBSP1_BASE,
		.dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
		.dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
		.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
		.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
		.ops = &omap2_mcbsp_ops,
		},
		{
		.phys_base = OMAP44XX_MCBSP2_BASE,
		.dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
		.dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
		.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
		.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
		.ops = &omap2_mcbsp_ops,
		},
		{
		.phys_base = OMAP44XX_MCBSP3_BASE,
		.dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
		.dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
		.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
		.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
		.ops = &omap2_mcbsp_ops,
		},
		{
		.phys_base = OMAP44XX_MCBSP4_BASE,
		.dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
		.dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
		.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
		.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
		.ops = &omap2_mcbsp_ops,
		},
		};
		#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)

		static int __init omap2_mcbsp_init(void)
		{
		if (cpu_is_omap2420())
		@@ -177,6 +213,8 @@ static int __init omap2_mcbsp_init(void)
		omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
		if (cpu_is_omap34xx())
		omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
		if (cpu_is_omap44xx())
		omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;

		mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
		GFP_KERNEL);
		@@ -192,6 +230,9 @@ static int __init omap2_mcbsp_init(void)
		if (cpu_is_omap34xx())
		omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
		OMAP34XX_MCBSP_PDATA_SZ);
		if (cpu_is_omap44xx())
		omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
		OMAP44XX_MCBSP_PDATA_SZ);

		return omap_mcbsp_init();
		}

arch/arm/mach-omap2/serial.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -97,6 +97,16 @@ static struct plat_serial8250_port serial_platform_data[] = {
		.regshift = 2,
		.uartclk = OMAP24XX_BASE_BAUD * 16,
		}, {
		#ifdef CONFIG_ARCH_OMAP4
		.membase = IO_ADDRESS(OMAP_UART4_BASE),
		.mapbase = OMAP_UART4_BASE,
		.irq = 70,
		.flags = UPF_BOOT_AUTOCONF,
		.iotype = UPIO_MEM,
		.regshift = 2,
		.uartclk = OMAP24XX_BASE_BAUD * 16,
		}, {
		#endif
		.flags = 0
		}
		};

arch/arm/plat-omap/gpio.c

+198 −51

Original line number	Diff line number	Diff line
		@@ -138,6 +138,32 @@
		#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
		#define OMAP24XX_GPIO_SETDATAOUT 0x0094

		#define OMAP4_GPIO_REVISION 0x0000
		#define OMAP4_GPIO_SYSCONFIG 0x0010
		#define OMAP4_GPIO_EOI 0x0020
		#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
		#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
		#define OMAP4_GPIO_IRQSTATUS0 0x002c
		#define OMAP4_GPIO_IRQSTATUS1 0x0030
		#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
		#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
		#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
		#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
		#define OMAP4_GPIO_IRQWAKEN0 0x0044
		#define OMAP4_GPIO_IRQWAKEN1 0x0048
		#define OMAP4_GPIO_SYSSTATUS 0x0104
		#define OMAP4_GPIO_CTRL 0x0130
		#define OMAP4_GPIO_OE 0x0134
		#define OMAP4_GPIO_DATAIN 0x0138
		#define OMAP4_GPIO_DATAOUT 0x013c
		#define OMAP4_GPIO_LEVELDETECT0 0x0140
		#define OMAP4_GPIO_LEVELDETECT1 0x0144
		#define OMAP4_GPIO_RISINGDETECT 0x0148
		#define OMAP4_GPIO_FALLINGDETECT 0x014c
		#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
		#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
		#define OMAP4_GPIO_CLEARDATAOUT 0x0190
		#define OMAP4_GPIO_SETDATAOUT 0x0194
		/*
		* omap34xx specific GPIO registers
		*/
		@@ -386,11 +412,15 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
		reg += OMAP850_GPIO_DIR_CONTROL;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_OE;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP4)
		case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_OE;
		break;
		#endif
		default:
		WARN_ON(1);
		@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
		l &= ~(1 << gpio);
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		if (enable)
		reg += OMAP24XX_GPIO_SETDATAOUT;
		@@ -468,6 +497,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
		reg += OMAP24XX_GPIO_CLEARDATAOUT;
		l = 1 << gpio;
		break;
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
		if (enable)
		reg += OMAP4_GPIO_SETDATAOUT;
		else
		reg += OMAP4_GPIO_CLEARDATAOUT;
		l = 1 << gpio;
		break;
		#endif
		default:
		WARN_ON(1);
		@@ -511,11 +549,15 @@ static int __omap_get_gpio_datain(int gpio)
		reg += OMAP850_GPIO_DATA_INPUT;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_DATAIN;
		break;
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_DATAIN;
		break;
		#endif
		default:
		return -EINVAL;
		@@ -544,7 +586,11 @@ void omap_set_gpio_debounce(int gpio, int enable)

		bank = get_gpio_bank(gpio);
		reg = bank->base;
		#ifdef CONFIG_ARCH_OMAP4
		reg += OMAP4_GPIO_DEBOUNCENABLE;
		#else
		reg += OMAP24XX_GPIO_DEBOUNCE_EN;
		#endif

		spin_lock_irqsave(&bank->lock, flags);
		val = __raw_readl(reg);
		@@ -581,7 +627,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
		reg = bank->base;

		enc_time &= 0xff;
		#ifdef CONFIG_ARCH_OMAP4
		reg += OMAP4_GPIO_DEBOUNCINGTIME;
		#else
		reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
		#endif
		__raw_writel(enc_time, reg);
		}
		EXPORT_SYMBOL(omap_set_gpio_debounce_time);
		@@ -593,7 +643,18 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
		{
		void __iomem *base = bank->base;
		u32 gpio_bit = 1 << gpio;
		u32 val;

		if (cpu_is_omap44xx()) {
		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
		trigger & IRQ_TYPE_LEVEL_LOW);
		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
		trigger & IRQ_TYPE_LEVEL_HIGH);
		MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
		trigger & IRQ_TYPE_EDGE_RISING);
		MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
		trigger & IRQ_TYPE_EDGE_FALLING);
		} else {
		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
		trigger & IRQ_TYPE_LEVEL_LOW);
		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
		@@ -602,14 +663,26 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
		trigger & IRQ_TYPE_EDGE_RISING);
		MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
		trigger & IRQ_TYPE_EDGE_FALLING);

		}
		if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
		if (cpu_is_omap44xx()) {
		if (trigger != 0)
		__raw_writel(1 << gpio, bank->base+
		OMAP4_GPIO_IRQWAKEN0);
		else {
		val = __raw_readl(bank->base +
		OMAP4_GPIO_IRQWAKEN0);
		__raw_writel(val & (~(1 << gpio)), bank->base +
		OMAP4_GPIO_IRQWAKEN0);
		}
		} else {
		if (trigger != 0)
		__raw_writel(1 << gpio, bank->base
		+ OMAP24XX_GPIO_SETWKUENA);
		else
		__raw_writel(1 << gpio, bank->base
		+ OMAP24XX_GPIO_CLEARWKUENA);
		}
		} else {
		if (trigger != 0)
		bank->enabled_non_wakeup_gpios \|= gpio_bit;
		@@ -617,10 +690,16 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
		bank->enabled_non_wakeup_gpios &= ~gpio_bit;
		}

		if (cpu_is_omap44xx()) {
		bank->level_mask =
		__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) \|
		__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
		} else {
		bank->level_mask =
		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) \|
		__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
		}
		}
		#endif

		static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
		@@ -783,11 +862,15 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
		reg += OMAP850_GPIO_INT_STATUS;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_IRQSTATUS1;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP4)
		case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_IRQSTATUS0;
		break;
		#endif
		default:
		WARN_ON(1);
		@@ -798,12 +881,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
		/* Workaround for clearing DSP GPIO interrupts to allow retention */
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
		if (cpu_is_omap24xx() \|\| cpu_is_omap34xx())
		#endif
		#if defined(CONFIG_ARCH_OMAP4)
		reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
		#endif
		if (cpu_is_omap24xx() \|\| cpu_is_omap34xx() \|\| cpu_is_omap44xx()) {
		__raw_writel(gpio_mask, reg);

		/* Flush posted write for the irq status to avoid spurious interrupts */
		__raw_readl(reg);
		#endif
		}
		}

		static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
		@@ -853,12 +940,17 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
		inv = 1;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_IRQENABLE1;
		mask = 0xffffffff;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP4)
		case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_IRQSTATUSSET0;
		mask = 0xffffffff;
		break;
		#endif
		default:
		WARN_ON(1);
		@@ -927,8 +1019,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
		l \|= gpio_mask;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		if (enable)
		reg += OMAP24XX_GPIO_SETIRQENABLE1;
		@@ -936,6 +1027,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
		reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
		l = gpio_mask;
		break;
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
		if (enable)
		reg += OMAP4_GPIO_IRQSTATUSSET0;
		else
		reg += OMAP4_GPIO_IRQSTATUSCLR0;
		l = gpio_mask;
		break;
		#endif
		default:
		WARN_ON(1);
		@@ -1112,10 +1212,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
		if (bank->method == METHOD_GPIO_850)
		isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		if (bank->method == METHOD_GPIO_24XX)
		isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
		#endif
		#if defined(CONFIG_ARCH_OMAP4)
		if (bank->method == METHOD_GPIO_24XX)
		isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
		#endif
		while(1) {
		u32 isr_saved, level_mask = 0;
		@@ -1547,7 +1650,7 @@ static int __init _omap_gpio_init(void)

		gpio_bank_count = OMAP34XX_NR_GPIOS;
		gpio_bank = gpio_bank_44xx;
		rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
		rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
		printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
		(rev >> 4) & 0x0f, rev & 0x0f);
		}
		@@ -1581,7 +1684,16 @@ static int __init _omap_gpio_init(void)
		static const u32 non_wakeup_gpios[] = {
		0xe203ffc0, 0x08700040
		};

		if (cpu_is_omap44xx()) {
		__raw_writel(0xffffffff, bank->base +
		OMAP4_GPIO_IRQSTATUSCLR0);
		__raw_writew(0x0015, bank->base +
		OMAP4_GPIO_SYSCONFIG);
		__raw_writel(0x00000000, bank->base +
		OMAP4_GPIO_DEBOUNCENABLE);
		/* Initialize interface clock ungated, module enabled */
		__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
		} else {
		__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
		__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
		__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
		@@ -1589,12 +1701,12 @@ static int __init _omap_gpio_init(void)

		/* Initialize interface clock ungated, module enabled */
		__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
		}
		if (i < ARRAY_SIZE(non_wakeup_gpios))
		bank->non_wakeup_gpios = non_wakeup_gpios[i];
		gpio_count = 32;
		}
		#endif

		/* REVISIT eventually switch from OMAP-specific gpio structs
		* over to the generic ones
		*/
		@@ -1680,13 +1792,19 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
		wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
		wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
		wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
		break;
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
		wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
		wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
		wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
		break;
		#endif
		default:
		continue;
		@@ -1722,12 +1840,17 @@ static int omap_gpio_resume(struct sys_device *dev)
		wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
		break;
		#endif
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		case METHOD_GPIO_24XX:
		wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
		wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
		break;
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
		wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
		wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
		break;
		#endif
		default:
		continue;
		@@ -1772,20 +1895,28 @@ void omap2_gpio_prepare_for_retention(void)

		if (!(bank->enabled_non_wakeup_gpios))
		continue;
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
		l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		bank->saved_datain = __raw_readl(bank->base +
		OMAP4_GPIO_DATAIN);
		l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
		l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
		#endif
		bank->saved_fallingdetect = l1;
		bank->saved_risingdetect = l2;
		l1 &= ~bank->enabled_non_wakeup_gpios;
		l2 &= ~bank->enabled_non_wakeup_gpios;
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		__raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		__raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
		__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
		#endif
		c++;
		}
		@@ -1808,33 +1939,49 @@ void omap2_gpio_resume_after_retention(void)

		if (!(bank->enabled_non_wakeup_gpios))
		continue;
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		__raw_writel(bank->saved_fallingdetect,
		bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		__raw_writel(bank->saved_risingdetect,
		bank->base + OMAP24XX_GPIO_RISINGDETECT);
		l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		__raw_writel(bank->saved_fallingdetect,
		bank->base + OMAP4_GPIO_FALLINGDETECT);
		__raw_writel(bank->saved_risingdetect,
		bank->base + OMAP4_GPIO_RISINGDETECT);
		l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
		#endif
		/* Check if any of the non-wakeup interrupt GPIOs have changed
		* state. If so, generate an IRQ by software. This is
		* horribly racy, but it's the best we can do to work around
		* this silicon bug. */
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
		#endif
		l ^= bank->saved_datain;
		l &= bank->non_wakeup_gpios;
		if (l) {
		u32 old0, old1;
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
		defined(CONFIG_ARCH_OMAP4)
		#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
		old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
		old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
		__raw_writel(old0 \| l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
		__raw_writel(old1 \| l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
		__raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
		__raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
		#endif
		#ifdef CONFIG_ARCH_OMAP4
		old0 = __raw_readl(bank->base +
		OMAP4_GPIO_LEVELDETECT0);
		old1 = __raw_readl(bank->base +
		OMAP4_GPIO_LEVELDETECT1);
		__raw_writel(old0 \| l, bank->base +
		OMAP4_GPIO_LEVELDETECT0);
		__raw_writel(old1 \| l, bank->base +
		OMAP4_GPIO_LEVELDETECT1);
		__raw_writel(old0, bank->base +
		OMAP4_GPIO_LEVELDETECT0);
		__raw_writel(old1, bank->base +
		OMAP4_GPIO_LEVELDETECT1);
		#endif
		}
		}

arch/arm/plat-omap/include/mach/dma.h

+88 −0

Original line number	Diff line number	Diff line
		@@ -122,6 +122,11 @@
		#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
		#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)

		/* Additional registers available on OMAP4 */
		#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
		#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
		#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)

		/* Dummy defines to keep multi-omap compiles happy */
		#define OMAP1_DMA_REVISION 0
		#define OMAP1_DMA_IRQSTATUS_L0 0
		@@ -311,6 +316,89 @@
		#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
		#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */

		/* DMA request lines for 44xx */
		#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
		#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
		#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
		#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
		#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
		#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
		#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
		#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
		#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
		#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
		#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
		#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
		#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
		#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
		#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
		#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
		#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
		#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
		#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
		#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
		#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
		#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
		#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
		#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
		#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
		#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
		#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
		#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
		#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
		#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
		#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
		#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
		#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
		#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
		#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
		#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
		#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
		#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
		#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
		#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
		#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
		#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
		#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
		#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
		#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
		#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
		#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
		#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
		#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
		#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
		#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
		#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
		#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
		#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
		#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
		#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
		#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
		#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
		#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
		#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
		#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
		#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
		#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
		#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
		#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
		#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
		#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
		#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
		#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
		#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
		#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
		#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
		#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
		#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
		#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
		#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
		#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
		#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
		#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
		#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
		#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */

		/----------------------------------------------------------------------------/

		/* Hardware registers for LCD DMA */