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Commit 61e72bca authored by Ryan Mallon's avatar Ryan Mallon Committed by Russell King
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ARM: 6935/1: SPEAR3xx: Rename register/irq defines to remove naming conflicts 



Prefix register and irq defintions to remove naming conflicts between
the three SPEAr3xx platforms.

Reviewed-by: default avatarStanley Miao <stanley.miao@windriver.com>
Signed-off-by: default avatarRyan Mallon <ryan@bluewatersys.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent f6558bf9

arch/arm/mach-spear3xx/include/mach/generic.h

+2 −2
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ 
 * Following GPT channels will be used as clock source and clockevent

 */

#define SPEAR_GPT0_BASE		SPEAR3XX_ML1_TMR_BASE

#define SPEAR_GPT0_CHAN0_IRQ	IRQ_CPU_GPT1_1

#define SPEAR_GPT0_CHAN1_IRQ	IRQ_CPU_GPT1_2

#define SPEAR_GPT0_CHAN0_IRQ	SPEAR3XX_IRQ_CPU_GPT1_1

#define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2



/* Add spear3xx family device structure declarations here */

extern struct amba_device gpio_device;

arch/arm/mach-spear3xx/include/mach/irqs.h

+104 −102
Original line number Diff line number Diff line
@@ -15,138 +15,140 @@ 
#define __MACH_IRQS_H



/* SPEAr3xx IRQ definitions */

#define IRQ_HW_ACCEL_MOD_0			0

#define IRQ_INTRCOMM_RAS_ARM			1

#define IRQ_CPU_GPT1_1				2

#define IRQ_CPU_GPT1_2				3

#define IRQ_BASIC_GPT1_1			4

#define IRQ_BASIC_GPT1_2			5

#define IRQ_BASIC_GPT2_1			6

#define IRQ_BASIC_GPT2_2			7

#define IRQ_BASIC_DMA				8

#define IRQ_BASIC_SMI				9

#define IRQ_BASIC_RTC				10

#define IRQ_BASIC_GPIO				11

#define IRQ_BASIC_WDT				12

#define IRQ_DDR_CONTROLLER			13

#define IRQ_SYS_ERROR				14

#define IRQ_WAKEUP_RCV				15

#define IRQ_JPEG				16

#define IRQ_IRDA				17

#define IRQ_ADC					18

#define IRQ_UART				19

#define IRQ_SSP					20

#define IRQ_I2C					21

#define IRQ_MAC_1				22

#define IRQ_MAC_2				23

#define IRQ_USB_DEV				24

#define IRQ_USB_H_OHCI_0			25

#define IRQ_USB_H_EHCI_0			26

#define IRQ_USB_H_EHCI_1			IRQ_USB_H_EHCI_0

#define IRQ_USB_H_OHCI_1			27

#define IRQ_GEN_RAS_1				28

#define IRQ_GEN_RAS_2				29

#define IRQ_GEN_RAS_3				30

#define IRQ_HW_ACCEL_MOD_1			31

#define IRQ_VIC_END				32



#define VIRQ_START				IRQ_VIC_END

#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0		0

#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM		1

#define SPEAR3XX_IRQ_CPU_GPT1_1			2

#define SPEAR3XX_IRQ_CPU_GPT1_2			3

#define SPEAR3XX_IRQ_BASIC_GPT1_1		4

#define SPEAR3XX_IRQ_BASIC_GPT1_2		5

#define SPEAR3XX_IRQ_BASIC_GPT2_1		6

#define SPEAR3XX_IRQ_BASIC_GPT2_2		7

#define SPEAR3XX_IRQ_BASIC_DMA			8

#define SPEAR3XX_IRQ_BASIC_SMI			9

#define SPEAR3XX_IRQ_BASIC_RTC			10

#define SPEAR3XX_IRQ_BASIC_GPIO			11

#define SPEAR3XX_IRQ_BASIC_WDT			12

#define SPEAR3XX_IRQ_DDR_CONTROLLER		13

#define SPEAR3XX_IRQ_SYS_ERROR			14

#define SPEAR3XX_IRQ_WAKEUP_RCV			15

#define SPEAR3XX_IRQ_JPEG			16

#define SPEAR3XX_IRQ_IRDA			17

#define SPEAR3XX_IRQ_ADC			18

#define SPEAR3XX_IRQ_UART			19

#define SPEAR3XX_IRQ_SSP			20

#define SPEAR3XX_IRQ_I2C			21

#define SPEAR3XX_IRQ_MAC_1			22

#define SPEAR3XX_IRQ_MAC_2			23

#define SPEAR3XX_IRQ_USB_DEV			24

#define SPEAR3XX_IRQ_USB_H_OHCI_0		25

#define SPEAR3XX_IRQ_USB_H_EHCI_0		26

#define SPEAR3XX_IRQ_USB_H_EHCI_1		SPEAR3XX_IRQ_USB_H_EHCI_0

#define SPEAR3XX_IRQ_USB_H_OHCI_1		27

#define SPEAR3XX_IRQ_GEN_RAS_1			28

#define SPEAR3XX_IRQ_GEN_RAS_2			29

#define SPEAR3XX_IRQ_GEN_RAS_3			30

#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1		31

#define SPEAR3XX_IRQ_VIC_END			32



#define SPEAR3XX_VIRQ_START			SPEAR3XX_IRQ_VIC_END



/* SPEAr300 Virtual irq definitions */

#ifdef CONFIG_MACH_SPEAR300

/* IRQs sharing IRQ_GEN_RAS_1 */

#define VIRQ_IT_PERS_S				(VIRQ_START + 0)

#define VIRQ_IT_CHANGE_S			(VIRQ_START + 1)

#define VIRQ_I2S				(VIRQ_START + 2)

#define VIRQ_TDM				(VIRQ_START + 3)

#define VIRQ_CAMERA_L				(VIRQ_START + 4)

#define VIRQ_CAMERA_F				(VIRQ_START + 5)

#define VIRQ_CAMERA_V				(VIRQ_START + 6)

#define VIRQ_KEYBOARD				(VIRQ_START + 7)

#define VIRQ_GPIO1				(VIRQ_START + 8)

#define SPEAR300_VIRQ_IT_PERS_S			(SPEAR3XX_VIRQ_START + 0)

#define SPEAR300_VIRQ_IT_CHANGE_S		(SPEAR3XX_VIRQ_START + 1)

#define SPEAR300_VIRQ_I2S			(SPEAR3XX_VIRQ_START + 2)

#define SPEAR300_VIRQ_TDM			(SPEAR3XX_VIRQ_START + 3)

#define SPEAR300_VIRQ_CAMERA_L			(SPEAR3XX_VIRQ_START + 4)

#define SPEAR300_VIRQ_CAMERA_F			(SPEAR3XX_VIRQ_START + 5)

#define SPEAR300_VIRQ_CAMERA_V			(SPEAR3XX_VIRQ_START + 6)

#define SPEAR300_VIRQ_KEYBOARD			(SPEAR3XX_VIRQ_START + 7)

#define SPEAR300_VIRQ_GPIO1			(SPEAR3XX_VIRQ_START + 8)



/* IRQs sharing IRQ_GEN_RAS_3 */

#define IRQ_CLCD				IRQ_GEN_RAS_3

#define SPEAR300_IRQ_CLCD			SPEAR3XX_IRQ_GEN_RAS_3



/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */

#define IRQ_SDHCI				IRQ_INTRCOMM_RAS_ARM



/* GPIO pins virtual irqs */

#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 9)

#define SPEAR_GPIO1_INT_BASE			(SPEAR_GPIO_INT_BASE + 8)

#define SPEAR_GPIO_INT_END			(SPEAR_GPIO1_INT_BASE + 8)

#define SPEAR300_IRQ_SDHCI			SPEAR3XX_IRQ_INTRCOMM_RAS_ARM



/* SPEAr310 Virtual irq definitions */

#elif defined(CONFIG_MACH_SPEAR310)

/* IRQs sharing IRQ_GEN_RAS_1 */

#define VIRQ_SMII0				(VIRQ_START + 0)

#define VIRQ_SMII1				(VIRQ_START + 1)

#define VIRQ_SMII2				(VIRQ_START + 2)

#define VIRQ_SMII3				(VIRQ_START + 3)

#define VIRQ_WAKEUP_SMII0			(VIRQ_START + 4)

#define VIRQ_WAKEUP_SMII1			(VIRQ_START + 5)

#define VIRQ_WAKEUP_SMII2			(VIRQ_START + 6)

#define VIRQ_WAKEUP_SMII3			(VIRQ_START + 7)

#define SPEAR310_VIRQ_SMII0			(SPEAR3XX_VIRQ_START + 0)

#define SPEAR310_VIRQ_SMII1			(SPEAR3XX_VIRQ_START + 1)

#define SPEAR310_VIRQ_SMII2			(SPEAR3XX_VIRQ_START + 2)

#define SPEAR310_VIRQ_SMII3			(SPEAR3XX_VIRQ_START + 3)

#define SPEAR310_VIRQ_WAKEUP_SMII0		(SPEAR3XX_VIRQ_START + 4)

#define SPEAR310_VIRQ_WAKEUP_SMII1		(SPEAR3XX_VIRQ_START + 5)

#define SPEAR310_VIRQ_WAKEUP_SMII2		(SPEAR3XX_VIRQ_START + 6)

#define SPEAR310_VIRQ_WAKEUP_SMII3		(SPEAR3XX_VIRQ_START + 7)



/* IRQs sharing IRQ_GEN_RAS_2 */

#define VIRQ_UART1				(VIRQ_START + 8)

#define VIRQ_UART2				(VIRQ_START + 9)

#define VIRQ_UART3				(VIRQ_START + 10)

#define VIRQ_UART4				(VIRQ_START + 11)

#define VIRQ_UART5				(VIRQ_START + 12)

#define SPEAR310_VIRQ_UART1			(SPEAR3XX_VIRQ_START + 8)

#define SPEAR310_VIRQ_UART2			(SPEAR3XX_VIRQ_START + 9)

#define SPEAR310_VIRQ_UART3			(SPEAR3XX_VIRQ_START + 10)

#define SPEAR310_VIRQ_UART4			(SPEAR3XX_VIRQ_START + 11)

#define SPEAR310_VIRQ_UART5			(SPEAR3XX_VIRQ_START + 12)



/* IRQs sharing IRQ_GEN_RAS_3 */

#define VIRQ_EMI				(VIRQ_START + 13)

#define VIRQ_PLGPIO				(VIRQ_START + 14)

#define SPEAR310_VIRQ_EMI			(SPEAR3XX_VIRQ_START + 13)

#define SPEAR310_VIRQ_PLGPIO			(SPEAR3XX_VIRQ_START + 14)



/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */

#define VIRQ_TDM_HDLC				(VIRQ_START + 15)

#define VIRQ_RS485_0				(VIRQ_START + 16)

#define VIRQ_RS485_1				(VIRQ_START + 17)



/* GPIO pins virtual irqs */

#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 18)

#define SPEAR310_VIRQ_TDM_HDLC			(SPEAR3XX_VIRQ_START + 15)

#define SPEAR310_VIRQ_RS485_0			(SPEAR3XX_VIRQ_START + 16)

#define SPEAR310_VIRQ_RS485_1			(SPEAR3XX_VIRQ_START + 17)



/* SPEAr320 Virtual irq definitions */

#else

/* IRQs sharing IRQ_GEN_RAS_1 */

#define VIRQ_EMI				(VIRQ_START + 0)

#define VIRQ_CLCD				(VIRQ_START + 1)

#define VIRQ_SPP				(VIRQ_START + 2)

#define SPEAR320_VIRQ_EMI			(SPEAR3XX_VIRQ_START + 0)

#define SPEAR320_VIRQ_CLCD			(SPEAR3XX_VIRQ_START + 1)

#define SPEAR320_VIRQ_SPP			(SPEAR3XX_VIRQ_START + 2)



/* IRQs sharing IRQ_GEN_RAS_2 */

#define IRQ_SDHCI				IRQ_GEN_RAS_2

#define SPEAR320_IRQ_SDHCI			SPEAR3XX_IRQ_GEN_RAS_2



/* IRQs sharing IRQ_GEN_RAS_3 */

#define VIRQ_PLGPIO				(VIRQ_START + 3)

#define VIRQ_I2S_PLAY				(VIRQ_START + 4)

#define VIRQ_I2S_REC				(VIRQ_START + 5)

#define SPEAR320_VIRQ_PLGPIO			(SPEAR3XX_VIRQ_START + 3)

#define SPEAR320_VIRQ_I2S_PLAY			(SPEAR3XX_VIRQ_START + 4)

#define SPEAR320_VIRQ_I2S_REC			(SPEAR3XX_VIRQ_START + 5)



/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */

#define VIRQ_CANU				(VIRQ_START + 6)

#define VIRQ_CANL				(VIRQ_START + 7)

#define VIRQ_UART1				(VIRQ_START + 8)

#define VIRQ_UART2				(VIRQ_START + 9)

#define VIRQ_SSP1				(VIRQ_START + 10)

#define VIRQ_SSP2				(VIRQ_START + 11)

#define VIRQ_SMII0				(VIRQ_START + 12)

#define VIRQ_MII1_SMII1				(VIRQ_START + 13)

#define VIRQ_WAKEUP_SMII0			(VIRQ_START + 14)

#define VIRQ_WAKEUP_MII1_SMII1			(VIRQ_START + 15)

#define VIRQ_I2C				(VIRQ_START + 16)



/* GPIO pins virtual irqs */

#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 17)

#define SPEAR320_VIRQ_CANU			(SPEAR3XX_VIRQ_START + 6)

#define SPEAR320_VIRQ_CANL			(SPEAR3XX_VIRQ_START + 7)

#define SPEAR320_VIRQ_UART1			(SPEAR3XX_VIRQ_START + 8)

#define SPEAR320_VIRQ_UART2			(SPEAR3XX_VIRQ_START + 9)

#define SPEAR320_VIRQ_SSP1			(SPEAR3XX_VIRQ_START + 10)

#define SPEAR320_VIRQ_SSP2			(SPEAR3XX_VIRQ_START + 11)

#define SPEAR320_VIRQ_SMII0			(SPEAR3XX_VIRQ_START + 12)

#define SPEAR320_VIRQ_MII1_SMII1		(SPEAR3XX_VIRQ_START + 13)

#define SPEAR320_VIRQ_WAKEUP_SMII0		(SPEAR3XX_VIRQ_START + 14)

#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1		(SPEAR3XX_VIRQ_START + 15)

#define SPEAR320_VIRQ_I2C1			(SPEAR3XX_VIRQ_START + 16)



/*

 * GPIO pins virtual irqs

 * Use the lowest number for the GPIO virtual IRQs base on which subarchs

 * we have compiled in

 */

#if defined(CONFIG_MACH_SPEAR310)

#define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 18)

#elif defined(CONFIG_MACH_SPEAR320)

#define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 17)

#else

#define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 9)

#endif



/* PLGPIO Virtual IRQs */

#define SPEAR300_GPIO1_INT_BASE			(SPEAR3XX_GPIO_INT_BASE + 8)

#define SPEAR3XX_PLGPIO_COUNT	102



#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)

#define SPEAR_PLGPIO_INT_BASE			(SPEAR_GPIO_INT_BASE + 8)

#define SPEAR_GPIO_INT_END			(SPEAR_PLGPIO_INT_BASE + 102)

#define SPEAR3XX_PLGPIO_INT_BASE		(SPEAR3XX_GPIO_INT_BASE + 8)

#define SPEAR3XX_GPIO_INT_END			(SPEAR3XX_PLGPIO_INT_BASE + \

							SPEAR3XX_PLGPIO_COUNT)

#else

#define SPEAR3XX_GPIO_INT_END	(SPEAR300_GPIO1_INT_BASE + 8)

#endif



#define VIRQ_END				SPEAR_GPIO_INT_END

#define NR_IRQS					VIRQ_END

#define SPEAR3XX_VIRQ_END	SPEAR3XX_GPIO_INT_END

#define NR_IRQS			SPEAR3XX_VIRQ_END



#endif /* __MACH_IRQS_H */

arch/arm/mach-spear3xx/include/mach/spear300.h

+13 −13
Original line number Diff line number Diff line
@@ -20,19 +20,19 @@ 
#define SPEAR300_TELECOM_BASE		UL(0x50000000)



/* Interrupt registers offsets and masks */

#define INT_ENB_MASK_REG		0x54

#define INT_STS_MASK_REG		0x58

#define IT_PERS_S_IRQ_MASK		(1 << 0)

#define IT_CHANGE_S_IRQ_MASK		(1 << 1)

#define I2S_IRQ_MASK			(1 << 2)

#define TDM_IRQ_MASK			(1 << 3)

#define CAMERA_L_IRQ_MASK		(1 << 4)

#define CAMERA_F_IRQ_MASK		(1 << 5)

#define CAMERA_V_IRQ_MASK		(1 << 6)

#define KEYBOARD_IRQ_MASK		(1 << 7)

#define GPIO1_IRQ_MASK			(1 << 8)



#define SHIRQ_RAS1_MASK			0x1FF

#define SPEAR300_INT_ENB_MASK_REG	0x54

#define SPEAR300_INT_STS_MASK_REG	0x58

#define SPEAR300_IT_PERS_S_IRQ_MASK	(1 << 0)

#define SPEAR300_IT_CHANGE_S_IRQ_MASK	(1 << 1)

#define SPEAR300_I2S_IRQ_MASK		(1 << 2)

#define SPEAR300_TDM_IRQ_MASK		(1 << 3)

#define SPEAR300_CAMERA_L_IRQ_MASK	(1 << 4)

#define SPEAR300_CAMERA_F_IRQ_MASK	(1 << 5)

#define SPEAR300_CAMERA_V_IRQ_MASK	(1 << 6)

#define SPEAR300_KEYBOARD_IRQ_MASK	(1 << 7)

#define SPEAR300_GPIO1_IRQ_MASK		(1 << 8)



#define SPEAR300_SHIRQ_RAS1_MASK	0x1FF



#define SPEAR300_CLCD_BASE		UL(0x60000000)

#define SPEAR300_SDHCI_BASE		UL(0x70000000)

arch/arm/mach-spear3xx/include/mach/spear310.h

+22 −22
Original line number Diff line number Diff line
@@ -29,29 +29,29 @@ 
#define SPEAR310_SOC_CONFIG_BASE	UL(0xB4000000)



/* Interrupt registers offsets and masks */

#define INT_STS_MASK_REG		0x04

#define SMII0_IRQ_MASK			(1 << 0)

#define SMII1_IRQ_MASK			(1 << 1)

#define SMII2_IRQ_MASK			(1 << 2)

#define SMII3_IRQ_MASK			(1 << 3)

#define WAKEUP_SMII0_IRQ_MASK		(1 << 4)

#define WAKEUP_SMII1_IRQ_MASK		(1 << 5)

#define WAKEUP_SMII2_IRQ_MASK		(1 << 6)

#define WAKEUP_SMII3_IRQ_MASK		(1 << 7)

#define UART1_IRQ_MASK			(1 << 8)

#define UART2_IRQ_MASK			(1 << 9)

#define UART3_IRQ_MASK			(1 << 10)

#define UART4_IRQ_MASK			(1 << 11)

#define UART5_IRQ_MASK			(1 << 12)

#define EMI_IRQ_MASK			(1 << 13)

#define TDM_HDLC_IRQ_MASK		(1 << 14)

#define RS485_0_IRQ_MASK		(1 << 15)

#define RS485_1_IRQ_MASK		(1 << 16)

#define SPEAR310_INT_STS_MASK_REG	0x04

#define SPEAR310_SMII0_IRQ_MASK		(1 << 0)

#define SPEAR310_SMII1_IRQ_MASK		(1 << 1)

#define SPEAR310_SMII2_IRQ_MASK		(1 << 2)

#define SPEAR310_SMII3_IRQ_MASK		(1 << 3)

#define SPEAR310_WAKEUP_SMII0_IRQ_MASK	(1 << 4)

#define SPEAR310_WAKEUP_SMII1_IRQ_MASK	(1 << 5)

#define SPEAR310_WAKEUP_SMII2_IRQ_MASK	(1 << 6)

#define SPEAR310_WAKEUP_SMII3_IRQ_MASK	(1 << 7)

#define SPEAR310_UART1_IRQ_MASK		(1 << 8)

#define SPEAR310_UART2_IRQ_MASK		(1 << 9)

#define SPEAR310_UART3_IRQ_MASK		(1 << 10)

#define SPEAR310_UART4_IRQ_MASK		(1 << 11)

#define SPEAR310_UART5_IRQ_MASK		(1 << 12)

#define SPEAR310_EMI_IRQ_MASK		(1 << 13)

#define SPEAR310_TDM_HDLC_IRQ_MASK	(1 << 14)

#define SPEAR310_RS485_0_IRQ_MASK	(1 << 15)

#define SPEAR310_RS485_1_IRQ_MASK	(1 << 16)



#define SHIRQ_RAS1_MASK			0x000FF

#define SHIRQ_RAS2_MASK			0x01F00

#define SHIRQ_RAS3_MASK			0x02000

#define SHIRQ_INTRCOMM_RAS_MASK		0x1C000

#define SPEAR310_SHIRQ_RAS1_MASK	0x000FF

#define SPEAR310_SHIRQ_RAS2_MASK	0x01F00

#define SPEAR310_SHIRQ_RAS3_MASK	0x02000

#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK	0x1C000



#endif /* __MACH_SPEAR310_H */

arch/arm/mach-spear3xx/include/mach/spear320.h

+24 −24
Original line number Diff line number Diff line
@@ -36,31 +36,31 @@ 
#define SPEAR320_SOC_CONFIG_BASE	UL(0xB3000000)



/* Interrupt registers offsets and masks */

#define INT_STS_MASK_REG		0x04

#define INT_CLR_MASK_REG		0x04

#define INT_ENB_MASK_REG		0x08

#define GPIO_IRQ_MASK			(1 << 0)

#define I2S_PLAY_IRQ_MASK		(1 << 1)

#define I2S_REC_IRQ_MASK		(1 << 2)

#define EMI_IRQ_MASK			(1 << 7)

#define CLCD_IRQ_MASK			(1 << 8)

#define SPP_IRQ_MASK			(1 << 9)

#define SDHCI_IRQ_MASK			(1 << 10)

#define CAN_U_IRQ_MASK			(1 << 11)

#define CAN_L_IRQ_MASK			(1 << 12)

#define UART1_IRQ_MASK			(1 << 13)

#define UART2_IRQ_MASK			(1 << 14)

#define SSP1_IRQ_MASK			(1 << 15)

#define SSP2_IRQ_MASK			(1 << 16)

#define SMII0_IRQ_MASK			(1 << 17)

#define MII1_SMII1_IRQ_MASK		(1 << 18)

#define WAKEUP_SMII0_IRQ_MASK		(1 << 19)

#define WAKEUP_MII1_SMII1_IRQ_MASK	(1 << 20)

#define I2C1_IRQ_MASK			(1 << 21)

#define SPEAR320_INT_STS_MASK_REG		0x04

#define SPEAR320_INT_CLR_MASK_REG		0x04

#define SPEAR320_INT_ENB_MASK_REG		0x08

#define SPEAR320_GPIO_IRQ_MASK			(1 << 0)

#define SPEAR320_I2S_PLAY_IRQ_MASK		(1 << 1)

#define SPEAR320_I2S_REC_IRQ_MASK		(1 << 2)

#define SPEAR320_EMI_IRQ_MASK			(1 << 7)

#define SPEAR320_CLCD_IRQ_MASK			(1 << 8)

#define SPEAR320_SPP_IRQ_MASK			(1 << 9)

#define SPEAR320_SDHCI_IRQ_MASK			(1 << 10)

#define SPEAR320_CAN_U_IRQ_MASK			(1 << 11)

#define SPEAR320_CAN_L_IRQ_MASK			(1 << 12)

#define SPEAR320_UART1_IRQ_MASK			(1 << 13)

#define SPEAR320_UART2_IRQ_MASK			(1 << 14)

#define SPEAR320_SSP1_IRQ_MASK			(1 << 15)

#define SPEAR320_SSP2_IRQ_MASK			(1 << 16)

#define SPEAR320_SMII0_IRQ_MASK			(1 << 17)

#define SPEAR320_MII1_SMII1_IRQ_MASK		(1 << 18)

#define SPEAR320_WAKEUP_SMII0_IRQ_MASK		(1 << 19)

#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK	(1 << 20)

#define SPEAR320_I2C1_IRQ_MASK			(1 << 21)



#define SHIRQ_RAS1_MASK			0x000380

#define SHIRQ_RAS3_MASK			0x000007

#define SHIRQ_INTRCOMM_RAS_MASK		0x3FF800

#define SPEAR320_SHIRQ_RAS1_MASK		0x000380

#define SPEAR320_SHIRQ_RAS3_MASK		0x000007

#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK	0x3FF800



#endif /* __MACH_SPEAR320_H */